TSMC appears to have the clearest publicly documented lead in leading-edge process execution. The company says its N2 node entered high-volume manufacturing in the fourth quarter of 2025 with “good yield” and should ramp quickly in 2026. But TSMC has not published a numeric N2 wafer-yield percentage, so claims of a definitive yield win over Intel 18A or Samsung SF2 go beyond the evidence.
Samsung has disclosed mass production of first-generation 2nm products, while Intel says 18A entered production and is powering its Panther Lake products. The meaningful comparison is therefore process maturity, customer confidence, capacity and economics—not an apples-to-apples leaderboard of yield percentages.
What “yield target” actually means
Yield is not a single universal number. Different figures answer different manufacturing questions:
- Defect density: defects per unit of wafer area, useful for tracking process learning.
- Wafer yield: the percentage of wafers passing required process and reliability checks.
- Die yield: the percentage of potentially usable dies produced from a wafer.
- Functional yield: the share of dies that operate electrically.
- Binned yield: the share meeting a specified speed, power or performance grade.
- Economic yield: whether good dies can be produced at an acceptable cost after testing, repair, binning and packaging.
A reported percentage may describe SRAM test structures, a product-like test vehicle, a small die or one process layer. It may not represent a large commercial processor. Die area matters especially: a defect that barely affects a small mobile chip can scrap an entire large AI accelerator.
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That is why a secondary report citing 55% or 10% cannot automatically be compared with a company statement that a process has “good yield.” The test vehicle, die size, maturity date and definition must be known.
What TSMC has confirmed about N2
TSMC’s 2025 annual report says N2 entered high-volume manufacturing in the fourth quarter of 2025. It describes N2 yield as good and expects a fast ramp during 2026. The company says demand comes from both smartphones and high-performance-computing and artificial-intelligence products.
Those are significant execution signals, but “good yield” is a qualitative management assessment. The cited disclosure does not provide a precise N2 percentage target or current wafer-yield figure.
Nanosheets and the N2 roadmap
N2 is TSMC’s first production node using nanosheet transistors instead of the FinFET architecture used in its preceding generations. In its second-quarter 2025 earnings transcript, TSMC targeted, versus N3E, 10–15% higher speed at the same power, 25–30% lower power at the same speed and more than 15% higher chip density. These are company targets, not independent benchmarks across finished products.
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TSMC’s roadmap also schedules N2P and A16 for volume production in the second half of 2026, according to the annual report. A sequence of derivatives can help customers reuse design work and gives the foundry a broader platform than a single launch node.
Do not confuse A14’s reported figure with N2
Approximately 90% figures discussed in coverage of TSMC’s 2026 commentary apply to A14 internal product-like vehicles— including device performance and 256 Mb SRAM yield—not to N2 production. The distinction is explicit in the reported transcript coverage. There is no basis for calling 90% TSMC’s N2 yield.
Samsung SF2: real production, less transparent economics
Samsung’s fourth-quarter 2025 earnings presentation says first-generation 2nm products entered mass production in late 2025. Its first-quarter 2026 presentation describes plans to ramp second-generation 2nm mobile products in the second half of 2026, expand customer engagement and maintain high-performance-computing design-win momentum.
Samsung therefore has not “failed to launch 2nm.” It has disclosed commercial production and ongoing customer activity. What remains uncertain is how broad, stable and profitable that production is, because Samsung has not published a directly comparable current SF2 percentage yield in the cited materials.
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Samsung’s potential advantage is broader than logic yield alone. Its combination of logic, memory, packaging and HBM-related capabilities could matter to AI customers even if its standalone foundry economics trail TSMC.
Intel 18A: production is real, but the foundry test is broader
Intel says 18A entered production in 2025. The process combines RibbonFET gate-all-around transistors with PowerVia backside power delivery. Intel claims up to 15% better performance per watt and 30% greater chip density than Intel 3, as described in its Panther Lake announcement.
Panther Lake is Intel’s first client product built on 18A. Intel said high-volume production would ramp during 2025, with broad availability beginning in January 2026. Its VLSI Symposium update also says 18A-P entered risk production in June 2026.
Intel disclosed use of High-NA EUV on selected Panther Lake layers in high-volume manufacturing in its second-quarter 2026 earnings release. That demonstrates equipment and process execution, but it does not establish a public 18A wafer-yield percentage.
How to treat the old 10% report
TrendForce summarized a Reuters report claiming Intel 18A yield was about 10% during mid-2025 risk production. Intel CFO David Zinsner disputed that figure and said yields were better, without publishing a replacement number. The report predates Intel’s subsequent production, product-launch and 2026 process updates. It should not be used as Intel’s current yield.
Intel’s captive product ramp gives 18A a different path from a merchant foundry. A successful internal product can build volume and learning, but external customers will also judge design rules, IP and EDA readiness, cost, delivery consistency and qualification history.
Why the node names are not equivalent
“N2,” “SF2” and “18A” are generation and marketing labels, not standardized physical measurements. Comparisons must account for:
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- transistor architecture and cell libraries;
- backside power delivery;
- EUV layer count and lithography strategy;
- SRAM scaling and each company’s density definition;
- performance and power targets;
- die size and product mix;
- packaging and chiplet configuration.
Use “2nm-class” or “leading-edge node” when discussing the group rather than implying identical transistor density or electrical characteristics.
Public evidence side by side
| Foundry | Node and architecture | Public production evidence | Public yield disclosure | Key unresolved issue |
|---|---|---|---|---|
| TSMC | N2 nanosheet; N2P and A16 follow-ons | High-volume manufacturing in Q4 2025; fast 2026 ramp expected | “Good yield”; no numeric N2 percentage | Scale, cost and large-die qualification during ramp |
| Samsung | SF2 2nm family | First-generation products in mass production in late 2025; second-generation mobile ramp planned for H2 2026 | Approximately 55% reported by TrendForce; not company-confirmed | Yield confidence, profitability, capacity and customer breadth |
| Intel | 18A RibbonFET with PowerVia | Production in 2025; Panther Lake ramp; 18A-P risk production in June 2026 | Older approximately 10% report disputed by Intel; no current official percentage | External foundry adoption, cost and delivery consistency |
What a yield gap means for customers and investors
Higher economic yield lowers the wafer cost per good die and improves the odds of supplying a product launch on schedule. It can influence wafer reservations, product gross margins, pricing and whether a foundry can accept external volume without disrupting internal programs.
Large AI accelerators make the economics less forgiving because their large area increases the chance that a defect makes a die unusable. A process adequate for a small mobile system-on-chip may not yet be economical for a large accelerator. Chiplets can reduce some risk by dividing functionality across smaller dies, but they add packaging, testing and interconnect requirements.
For customers, process leadership also includes packaging capacity, reliability, geographic diversity, design enablement, intellectual-property libraries and a record of shipping qualified silicon. A foundry can have strong transistor performance and still lose business if it cannot deliver those supporting capabilities.
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Is TSMC’s lead durable?
The strongest defensible conclusion is that TSMC leads in publicly documented high-volume ramp and execution confidence. Its N2 production date, qualitative yield statement, dual smartphone and AI/HPC demand and follow-on roadmap form a more complete public signal than a single anonymous yield estimate.
That does not guarantee victory. Intel has a captive Panther Lake ramp, differentiated backside power and U.S. manufacturing appeal. Samsung can package logic, memory and HBM capabilities into a system-level offer. TSMC still faces capacity expansion, EUV productivity, defect learning, packaging bottlenecks and customer qualification risks.
The practical scorecard is therefore multidimensional:
- confirmed production stage, from risk production to stable high-volume output;
- yield transparency and the relevance of the reported test vehicle;
- named products, tape-outs and repeat customer commitments;
- good-die cost, wafer pricing and packaging economics;
- performance, power, density and reliability;
- capacity, tools, IP, EDA support and delivery consistency.
On the evidence available through 2026, TSMC has the clearest lead on the first and most visible of those measures. Samsung and Intel have made genuine production progress, but the public record does not yet provide comparable proof that either is operating at TSMC-like scale and economics.
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