Google acquired Provino Technologies in early February 2021 in a transaction that included 20 patents and patent applications covering network-on-chip (NoC) communications and power control, according to IEEE Spectrum. The purchase price and legal structure were not disclosed. Google later confirmed the acquisition, while Provino’s website disappeared and several India-based engineers began listing Google as their employer.
The public record supports an acquisition centered on specialized intellectual property and engineering talent. It does not establish that Provino’s iFabric platform continued as a product or that its technology appeared in any particular Tensor Processing Unit (TPU).
What Google acquired
Provino was a semiconductor-design startup founded in 2015 by Shailendra Desai, described by IEEE Spectrum as a former Apple engineer. It operated in Silicon Valley and Ahmedabad, India, and developed iFabric, a platform intended to help teams build chips using network-on-chip architectures. Provino marketed the technology for machine-learning and artificial-intelligence systems, as well as consumer and automotive applications.
IEEE Spectrum reported that Google bought 20 Provino patents and patent applications in early February 2021 for an undisclosed sum. The filings related to NoC communications and power control. The same report said Provino’s website went offline around that time and that some India-based engineers began identifying themselves as Google employees. Google confirmed that it had acquired Provino but released no additional transaction details.
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Acquisition, asset purchase, or both?
It is safest to say that Google acquired Provino in a deal that included the disclosed patent portfolio. The available reporting does not reveal whether the legal transaction was a stock acquisition, an asset purchase, a combination of the two, or another arrangement.
- The purchase price is unknown.
- The number of employees who joined Google is unknown.
- There is no public confirmation that every Provino employee transferred.
- The fate of iFabric, Provino’s contracts, liabilities, and other assets was not disclosed.
- The 20 patents and patent applications may not represent all of the technology or know-how Google obtained.
Investor Lip-Bu Tan publicly congratulated Desai and the Provino team after the report, providing contextual support for the transaction’s significance, although a social-media post is not a substitute for deal documents. See his LinkedIn post.
What is a network-on-chip?
A network-on-chip is an internal communication system for a complex integrated circuit. Processing cores, memory controllers, accelerators, and I/O blocks send data through interconnected links and routers, often using packetized traffic. That differs from relying primarily on a shared bus, centralized interconnect, or a large collection of dedicated point-to-point wires.
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In an AI accelerator, arithmetic is only part of the workload. Thousands of processing elements may need to exchange activations, weights, partial results, and control messages. As the number of engines grows, moving data between them can limit throughput, consume substantial energy, and leave expensive compute units waiting.
Why the architecture can help
- Scalability: A structured network can connect many processing elements more systematically than a single shared bus.
- Concurrent traffic: Separate links can carry multiple transfers at the same time.
- Local wiring: Shorter hop-by-hop connections can be easier to implement than long global wires.
- Potential resilience: Multiple routes can allow traffic to avoid a failed link when the hardware and routing policy support it.
- Configurability: Topology and routing can be tailored to a chip’s dataflow and mix of compute, memory, and I/O blocks.
NoC is not automatically faster or more efficient. Results depend on topology, link width and frequency, routing algorithms, buffer sizes, traffic patterns, memory placement, and congestion behavior.
Why Google might want Provino’s expertise
Google has designed custom application-specific chips, including TPUs, for neural-network workloads. IEEE Spectrum noted that Google had been developing neural-network ASICs since 2015 and used TPUs in data centers supporting services such as Translate, Photos, Search, Assistant, and Gmail.
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In that context, NoC intellectual property could be strategically relevant as accelerator designs become larger and more heterogeneous. A capable on-chip interconnect might help a future design:
- Scale to more processing elements without making communication a central bottleneck.
- Keep parallel workloads supplied with data.
- Reduce energy spent moving information between nearby blocks.
- Connect compute cores, memory controllers, I/O, and specialized engines in one system.
- Offer alternate paths or traffic-management options when links become congested.
- Provide a reusable interconnect foundation across several custom-ASIC generations.
Those are engineering reasons the technology could have interested Google, not disclosed results of the acquisition. The public report identifies no TPU generation, tape-out, benchmark, chip diagram, or production deployment that uses Provino’s IP.
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Provino’s company and funding history
| Item | Reported detail |
|---|---|
| Founded | 2015 |
| Founder | Shailendra Desai |
| Product | iFabric, a development platform for NoC-based chips |
| Locations | Silicon Valley and Ahmedabad, India |
| Target markets | Machine learning and AI, consumer electronics, and automotive |
| Funding | $8 million Series A in 2018 |
| Series A lead | Dell Technologies Capital |
The $8 million figure is reported Series A funding, not a valuation, purchase price, or total lifetime financing. Dell Technologies Capital described Provino as addressing next-generation system-on-chip design for AI and machine-learning markets.
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Technical trade-offs Google would have to evaluate
An NoC is a design framework, not a guaranteed performance upgrade. Engineers must match the network to the workload and physical constraints of the chip.
Measures that matter
- Average and worst-case communication latency.
- Sustained aggregate bandwidth under training and inference traffic.
- Energy per bit moved.
- Router area, buffer overhead, and timing impact.
- Congestion behavior during bursts and collective operations.
- Fault detection and rerouting capability.
- Ease of physical implementation and timing closure.
- Compiler and software support for mapping workloads onto the topology.
- Compatibility with HBM, chiplets, external I/O, and memory-coherence requirements.
Where NoC designs can fail
Routers consume area and power, while routing decisions and buffering add latency and control complexity. Buffers can absorb bursts but enlarge the die; more sophisticated routing can improve utilization while increasing verification and energy costs. A topology optimized for neural-network dataflow may be a poor fit for other workloads. Congestion can erase theoretical bandwidth, and fault tolerance requires monitoring, spare paths, and routing policies rather than appearing automatically.
IEEE Spectrum cited an academic expert who highlighted open questions involving router design, routing algorithms, buffers, link capacity, and wider architectural and algorithmic challenges. An NoC also does not remove memory-bandwidth, packaging, thermal, or algorithmic limits.
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What the deal says about Google’s chip strategy—and what it does not
The acquisition is a credible signal that advanced on-chip communication mattered to Google’s custom-silicon work in 2021. Buying a small specialist can provide patents, design methods, and experienced engineers faster than building an equivalent capability internally. It can also preserve options for future accelerator architectures even if a startup’s standalone software platform is not commercially viable.
That signal should not be turned into a product claim. The evidence does not show that Google redesigned a TPU because of Provino, that all TPUs use NoC technology, or that the deal produced lower energy use or higher performance. Nor does the 20-item patent count measure the complete value of Provino’s engineering knowledge.
Timeline and evidence boundary
| When | What is established |
|---|---|
| 2015 | Provino founded by Shailendra Desai. |
| 2018 | Provino raised an $8 million Series A led by Dell Technologies Capital. |
| Early February 2021 | IEEE Spectrum reported Google’s purchase of 20 patents and patent applications; Provino’s site went offline and some engineers moved to Google. |
| May 7, 2021 | IEEE Spectrum published its account; Google confirmed the acquisition without disclosing further terms. |
| After publication | Lip-Bu Tan posted a public congratulations to Desai and the Provino team. |
This history describes a 2021 transaction. It does not establish Provino’s operating status in 2026 or Google’s present-day architecture.
Bottom line for investors and chip watchers
Google acquired Provino in a deal that included 20 NoC-related patents and patent applications, but the company did not disclose the price or legal mechanics. The combination of transferred IP, apparent employee moves, and Google’s confirmation points to a talent-and-technology acquisition rather than a publicly documented product launch.
Network-on-chip technology addresses a real scaling problem in AI hardware: moving data among growing numbers of compute and memory blocks. Whether Provino’s work improved a Google accelerator remains unverified. The acquisition is therefore best read as an option on interconnect expertise—not proof of a specific TPU redesign or a measured performance gain.
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