Short answer: the underlying development is real, but “SMIC is building a 5nm chip for Huawei without EUV” is too broad. Independent chip analysis has linked Huawei’s Kirin 9000S to SMIC’s 7nm-class N+2 process and its later Kirin 9030 to SMIC’s N+3 process. N+3 is a meaningful advance and may approach 5nm-class performance on selected measures, but it is not established as equivalent to TSMC’s or Samsung’s conventional 5nm processes.
SMIC also is the world’s third-largest pure-play foundry by revenue in recent TrendForce rankings. That ranking measures business scale, not leading-edge process leadership.
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What actually happened?
Two related developments are often compressed into one sensational headline.
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Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →- Kirin 9000S: TechInsights identified Huawei’s smartphone chip as being manufactured by SMIC on a 7nm-class N+2 process. The analysis found no evidence that EUV lithography was used.
- Kirin 9030: TechInsights later identified the newer Huawei chip as using SMIC’s N+3 process, described as a scaled extension of the earlier 7nm-class technology.
That chronology matters. A completed commercial chip is evidence of a manufacturing capability. It is not automatically proof that SMIC has a broadly available, high-yield 5nm platform or that every future Huawei chip will be manufactured at that level.
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TechInsights’ Kirin 9000S analysis provides the strongest public evidence for the N+2 milestone. Its later Kirin 9030 analysis links that chip to N+3.
What do N+2 and N+3 mean?
SMIC’s N+2 and N+3 labels describe successive process improvements within its own technology family. They are not universal industry measurements and should not be treated as direct synonyms for TSMC N5 or Samsung’s 5nm-class processes.
Modern node names are shorthand for much more than one physical feature size. Relevant measures include transistor density, gate pitch, metal pitch, SRAM scaling, power, performance, design rules, yield and cost. Two foundries can use the same nominal node label while offering materially different characteristics.
| Question | What the evidence supports |
|---|---|
| Is N+3 newer than SMIC N+2? | Yes. It is a subsequent improvement to the process family. |
| Can some N+3 measurements approach 5nm-class benchmarks? | Independent analyses indicate that selected density or pitch metrics can be competitive or close. |
| Is N+3 identical to TSMC N5 or Samsung 5nm? | No. The available evidence does not establish that equivalence. |
| Does a similar density prove identical efficiency, yield or cost? | No. Those require separate measurements and production evidence. |
| Is a broad, high-yield commercial 5nm-equivalent platform publicly proven? | Not conclusively. |
Independent reporting has characterized N+3 as more advanced than SMIC’s original 7nm-class process while still behind leading commercial 5nm nodes overall. Reuters coverage described the Kirin 9030 as using an improved SMIC process rather than demonstrating straightforward parity with foreign 5nm technology. Additional teardown reporting drawing on SemiAnalysis offers comparisons of density and metal pitch, but those comparisons do not turn N+3 into an official TSMC N5 equivalent.
How can DUV make such advanced chips without EUV?
“Without EUV” means without extreme ultraviolet lithography. It does not mean without foreign equipment or without advanced lithography.
Deep ultraviolet, or DUV, immersion lithography commonly uses a 193-nanometer wavelength. At advanced nodes, a single DUV exposure cannot print every critical feature at the required dimensions. Manufacturers can instead split the pattern across multiple exposures and process steps.
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Those methods can include self-aligned multiple patterning, quadruple patterning, computational lithography, restrictive design rules and design-technology co-optimization. In simplified terms:
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- A pattern is divided into several compatible layers.
- DUV tools expose those layers repeatedly.
- Deposition, etching and alignment steps combine the results into smaller structures.
- The chip is tested and defective dies are discarded.
This approach can work, but the trade-off is substantial. More exposures mean more masks, more deposition and etch steps, longer wafer cycle times, more opportunities for alignment errors and defects, and greater engineering complexity.
EUV is therefore not physically mandatory for every structure sometimes described as “5nm-class.” Its advantage is that it makes advanced patterning more practical and economical, with fewer patterning steps for critical layers. DUV can substitute for some EUV work, but usually with higher process burden and weaker economics.
Importantly, DUV-based production may still rely on imported lithography tools, materials, photoresists, metrology systems, components, electronic design automation and other supply-chain inputs. “No EUV” should not be read as “no foreign technology.” A Congressional hearing document on China’s semiconductor capabilities discusses the role of DUV equipment and the broader equipment challenge.
Is SMIC’s N+3 process a real 5nm process?
Not in the straightforward commercial sense suggested by the headline.
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A chip’s real-world result also depends on architecture, clock speeds, packaging, memory subsystem, software and power limits. Even if two chips use processes with comparable dimensions, they may deliver different performance and efficiency.
What remains unknown about cost, yield and volume?
The strategic achievement is visible; the manufacturing economics are much less certain.
DUV multi-patterning can increase:
- the number of lithography exposures and masks;
- deposition, etch and inspection steps;
- wafer cycle time;
- defect opportunities;
- engineering and verification work;
- difficulty scaling SRAM, analog and input/output circuitry; and
- the cost per usable die if yield is lower.
A larger die or lower transistor density can also reduce the number of chips obtained from each wafer. That matters especially for large AI accelerators, where a modest defect-rate penalty can have a much larger effect on cost than it does for a smaller smartphone processor.
TrendForce reported an industry estimate that a DUV-based SMIC 5nm effort could cost roughly 50% more than TSMC’s equivalent effort. That is an attributed estimate, not an audited SMIC figure. No precise public yield percentage should be assumed from it.
Likewise, the existence of commercially shipped Kirin chips does not by itself reveal wafer allocation, monthly capacity, yield, pricing or profitability. A process can be commercially usable for a selected product while remaining more expensive or capacity-constrained than a competing foreign process.
What does “for Huawei” mean?
The public evidence supports a manufacturing relationship between Huawei and SMIC, but “for Huawei” can describe several different arrangements:
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- Huawei designs the chip and SMIC manufactures it.
- Huawei provides important demand that helps support process development and production.
- SMIC develops a process that could eventually serve more than one customer.
The Kirin chips strongly support the first interpretation for those products. Public reporting does not establish every detail of production volume, wafer allocation, yield or pricing. Nor should a report about a planned or rumored chip be merged with the verified analysis of a chip that has already been examined.
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SMIC’s third-place ranking is genuine when the category is defined correctly: pure-play foundry revenue.
TrendForce ranked SMIC third in its fourth-quarter 2025 foundry ranking, with approximately $2.49 billion in quarterly foundry revenue. It also retained third place in the first-quarter 2026 ranking, with approximately 5.1% market share. Because foundry rankings change by quarter, “third largest” should always carry a date.
That ranking does not mean SMIC has the third-best leading-edge process. Revenue reflects the whole business, including mature-node and specialty-node production, domestic customers, utilization and localization demand. China’s semiconductor policies and customer preference for domestic supply also support SMIC’s market position.
TSMC and Samsung have much stronger positions in advanced-node manufacturing, where high-value smartphone, computing and AI products generate significant revenue. A company can therefore rank third by total foundry revenue while remaining substantially behind the leaders in leading-edge process technology.
See the TrendForce 4Q25 ranking and TrendForce 1Q26 ranking for the dated market-share data.
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Why the development matters geopolitically
U.S. export restrictions have limited China’s access to the most advanced semiconductor equipment and related design resources. The Kirin 9000S and Kirin 9030 evidence shows that those restrictions can slow progress and raise its cost without making all advanced-chip development impossible.
SMIC’s work demonstrates adaptation: process innovation, repeated DUV patterning, close coordination between chip design and manufacturing, and the use of domestic demand to sustain difficult production. It does not demonstrate unrestricted access to leading-edge tools or manufacturing parity with TSMC and Samsung.
The more consequential question is whether China can repeat the achievement at sufficient yield, cost, reliability and volume. Smartphone processors can tolerate economics that would be unacceptable for very large AI accelerators. The answer will depend on good-die cost, monthly capacity, defect rates, packaging, memory supply and the ability to build a wider domestic equipment and materials ecosystem.
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The most useful signals are not simply the next “5nm” headline. Watch for:
- physical teardowns identifying the process used in a completed chip;
- evidence of sustained volume production rather than a limited run;
- reported or disclosed wafer capacity and utilization;
- cost per good die and yield trends;
- power and performance comparisons at comparable designs;
- progress in SRAM, analog and other difficult chip blocks;
- domestic availability of lithography, etch, deposition, metrology, materials and EDA tools; and
- whether the process can serve larger and more economically demanding chips.
These indicators distinguish an engineering demonstration from a scalable manufacturing platform. For financial analysis, SMIC’s revenue ranking and process capability should therefore be treated as separate data points rather than evidence that one automatically proves the other.
Bottom line
SMIC has shown that China can continue moving toward 5nm-class logic using DUV lithography rather than EUV. TechInsights’ analyses of the Kirin 9000S and Kirin 9030 provide important physical evidence of progress from N+2 to N+3.
But the most accurate description is advanced DUV-based N+3 scaling, not proven full 5nm parity with TSMC or Samsung. The breakthrough is strategically significant, while its ultimate commercial importance depends on yield, cost, cycle time and volume. SMIC’s third-place foundry ranking is also real—but it is a revenue ranking, not a ranking of leading-edge technology.
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