Yes, the European Union is treating RISC-V as a strategic tool for greater chip sovereignty. In its June 3, 2026 technology sovereignty package, the European Commission proposed supporting open-source hardware IP, including RISC-V, through the proposed Chips Act 2.0. The Commission also says Europe has invested about €500 million in open RISC-V through the Chips Joint Undertaking.
But RISC-V is not a semiconductor factory, a finished processor, or a complete European supply chain. It can give European companies more control over processor design and reduce reliance on proprietary CPU licensing. It cannot, by itself, eliminate dependence on foreign fabrication plants, electronic-design-automation software, memory, packaging, or global supply chains.
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What the EU actually announced
The Commission’s European Technological Sovereignty Package, presented on June 3, 2026, combines several initiatives:
- a proposed Chips Act 2.0, intended to expand support for chip design, manufacturing, packaging, and advanced semiconductor capacity;
- a Cloud and AI Development Act aimed at strengthening European cloud and AI capabilities;
- an EU Open Source Strategy covering software and hardware;
- a proposed advanced-chip pilot combining leading-edge manufacturing, chiplet integration, and 2.5D/3D packaging; and
- greater support for European fabless chip companies, open processor IP, and electronic-design-automation tools.
The Commission describes the package as a response to Europe’s dependence on suppliers outside the EU for important digital technologies and to rising demand for AI and cloud infrastructure. The Chips Act 2.0 proposal remains a legislative proposal, not an enacted replacement for the 2023 European Chips Act. Its provisions may change during the legislative process. See the EUR-Lex proposal.
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What RISC-V is—and what it is not
RISC-V is an instruction-set architecture, or ISA. An ISA defines the instructions that a processor understands. It is comparable to a language or contract between software and processor hardware.
RISC-V is an open standard and is not controlled by a single commercial CPU licensor in the way proprietary architectures are. Its modular design also lets chip designers add extensions for workloads such as artificial intelligence, security, automotive processing, or high-performance computing.
That does not mean every RISC-V chip is open-source. These terms describe different layers:
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| Term | Meaning |
|---|---|
| Open ISA | The RISC-V instruction-set specification is available for use under its governing framework. |
| Open-source core | A particular processor implementation has source code available under an applicable open-source licence. |
| Commercial RISC-V core | A company sells a proprietary processor implementation that follows the RISC-V ISA. |
| RISC-V chip | A finished product that may combine a RISC-V core with proprietary accelerators, memory controllers, security blocks, firmware, and other IP. |
The technology stack is therefore better represented as:
ISA → processor core → system-on-chip → wafer fabrication → packaging and testing → firmware and operating system → finished product
RISC-V directly affects the first layer and may support the second. European policy must address every later layer if the goal is meaningful sovereignty.
Why RISC-V is strategically useful to Europe
Processor architecture is a strategically important part of modern technology. Chips used in cars, telecom equipment, cloud servers, industrial systems, defence platforms, medical devices, and AI infrastructure increasingly determine the capabilities and security of those products.
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An open ISA can help Europe in several ways:
- Less dependence on one proprietary licensor: European designers can build compatible processors without relying on a single company’s architecture licence.
- More design freedom: Teams can customise processor features for automotive, industrial, security, or scientific workloads.
- Lower barriers to experimentation: Universities, startups, public laboratories, and established chip companies can work from a common architecture.
- More inspectability: Where implementations are genuinely open, researchers and customers may be able to examine more of the design.
- Potentially stronger local expertise: Shared specifications, development tools, and training can help expand Europe’s processor-design workforce.
The Commission’s RISC-V and open-source hardware roadmap presents open hardware and software as ways to lower barriers to system-on-chip design and create alternatives to non-European processor IP suppliers.
RISC-V is not European property. It is an international standard used by organisations in many jurisdictions. The EU is using it as an instrument for European design autonomy; it does not own the architecture or control every RISC-V implementation.
Chip sovereignty is a spectrum
“Sovereignty” is not a binary condition. A country or region can control one layer of a technology stack while remaining dependent on other layers.
- Architectural sovereignty: control over the processor specification and freedom from dependence on one proprietary ISA licensor.
- Design sovereignty: control over processor cores, SoC designs, verification, firmware, and important IP.
- Manufacturing sovereignty: access to wafer fabrication, including both advanced and mature process technologies.
- Packaging and testing sovereignty: capacity for chiplet integration, advanced packaging, reliability testing, and secure handling.
- Supply-chain sovereignty: access to equipment, chemicals, substrates, memory, interconnects, and other components.
- Software sovereignty: compilers, operating systems, drivers, libraries, cloud support, and application compatibility.
- Operational sovereignty: the ability to audit, maintain, update, and replace systems during a geopolitical crisis.
RISC-V primarily addresses architectural and design sovereignty. It may contribute to software sovereignty, but it does not independently solve manufacturing, packaging, equipment, or supply-chain dependence.
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The Chips Joint Undertaking is a public-private implementation body supporting Europe’s electronic-components-and-systems value chain. It is not itself a chip manufacturer.
Its mechanisms include:
- Pilot lines: pre-commercial facilities where companies and researchers can validate semiconductor technologies and designs;
- a cloud-based design platform: shared access to chip-design infrastructure and tools;
- competence centres: regional access to expertise, prototyping, skills, and industrial support;
- research and innovation calls: programmes covering AI hardware, edge computing, cybersecurity, 6G, energy efficiency, packaging, photonics, and healthcare; and
- public-private co-funding: EU, participating-state, and industry contributions.
The Chips JU’s 2026 open calls included indicative EU budgets of €40 million for a high-technology-readiness-level call and €50 million for a lower-TRL research call, alongside other calls. These were broad semiconductor and electronic-systems opportunities, not automatically RISC-V-specific funding.
The European RISC-V ecosystem
European Processor Initiative
The European Processor Initiative, or EPI, is a long-running European processor-development effort involving processor, accelerator, software, and system work for strategic applications. It is a consortium and technology programme, not an EU-owned chip company.
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- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
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Its relevance to RISC-V lies in developing European capabilities across high-performance computing, automotive, embedded systems, and other sectors. EPI should not be treated as proof that Europe already controls a complete commercial processor supply chain.
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eProcessor
The eProcessor project reported the successful deployment in silicon of a European out-of-order RISC-V processor in 2025. According to RISC-V International’s project coverage, the chip was produced using a 22 nm process and ran Linux. The project involved organisations including Barcelona Supercomputing Center, Chalmers, Cortus, and Thales.
This is a significant engineering milestone, but it should be described accurately. It demonstrates that a European project reached silicon with an out-of-order RISC-V processor; it does not establish mass production, independent performance leadership, or commercial parity with mature Arm or x86 platforms.
Openchip
Openchip is a European RISC-V company and a Premier Member of RISC-V International. It illustrates the move from academic research toward commercial processor technology. Membership in RISC-V International does not by itself prove EU funding, European fabrication, or product competitiveness. Its relevance should be judged by actual designs, customers, manufacturing arrangements, and sustained commercial activity.
Codasip
Codasip, headquartered in Europe, supplies configurable RISC-V processor IP and processor-development tools. Its business demonstrates that European RISC-V sovereignty may involve commercial IP vendors as well as open-source projects.
Codasip’s products are commercial. They should not be described as fully open-source simply because they implement RISC-V. Commercial IP can provide production support, configuration, verification, and tooling, while retaining proprietary elements.
SiPearl and the wider processor effort
SiPearl is relevant to Europe’s broader processor sovereignty ambitions through server and high-performance-computing work. Not every European processor initiative is RISC-V-based, however. Europe is pursuing several processor and accelerator programmes, and RISC-V is one important strand rather than the entire strategy.
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What Chips Act 2.0 could change
The proposed Chips Act 2.0 would broaden support for the ecosystem surrounding chip design and manufacturing. Its RISC-V-related implications include:
- support for open-source processor IP;
- investment in open-source EDA tools;
- greater emphasis on European chip designers and fabless companies;
- co-design between chip designers, manufacturers, and end-user industries;
- strategic applications including automotive AI, defence, cloud infrastructure, and industrial systems; and
- support for advanced manufacturing, packaging, chiplets, and related infrastructure.
The proposal discusses RISC-V-based automotive application processors and expects strategic projects to include competitive RISC-V designs and supporting toolchains. Those are proposed policy directions, not evidence that a production-scale European RISC-V automotive processor has already entered the market.
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Manufacturing remains separate
A European company can design a RISC-V chip and manufacture it at a non-European foundry. That may deliver architectural and design autonomy while leaving manufacturing sovereignty elsewhere.
The Commission’s advanced-chip initiative estimates that its proposed pilot and related ecosystem could mobilise €20–40 billion. It also estimates that €3–4 billion could be mobilised for European fabless chip-design companies. These are future investment estimates, not amounts already spent. See the Commission’s advanced-chip overview.
EDA tools are a major bottleneck
Modern chips require tools for logic synthesis, place and route, timing analysis, simulation, formal verification, physical verification, and manufacturing preparation. Many leading EDA tools come from companies headquartered outside the EU.
Open-source EDA could reduce strategic dependence, but production-grade tools must also deliver accuracy, performance, support, interoperability, and qualification for real manufacturing processes. The existence of open tools does not automatically make a complete chip-design flow independent.
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Processor adoption requires more than an ISA and a successful tape-out. Buyers need mature compiler back ends, operating-system support, drivers, debugging and profiling tools, virtualization, optimised libraries, cloud integration, and long-term maintenance.
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Linux support is an important milestone. It is not the same as broad application compatibility or parity with the established software ecosystems surrounding Arm and x86.
Performance depends on implementation
RISC-V does not guarantee that a processor will be faster, cheaper, or more energy-efficient. Those outcomes depend on microarchitecture, cache and memory design, vector and matrix extensions, accelerators, compiler quality, process technology, packaging, cooling, and software optimisation.
Openness is not automatic security
Open designs may improve inspectability and make custom security features possible. Security still depends on correct implementation, secure boot, memory protection, isolation, side-channel resistance, trusted manufacturing, firmware maintenance, independent verification, and supply-chain integrity.
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Public funding can support prototypes, pilot lines, and research. Lasting sovereignty requires customers willing to buy the resulting products at competitive prices. Automotive companies, cloud providers, telecom operators, defence agencies, and industrial firms must commit to designs, provide recurring demand, and support products after grants expire.
How to interpret the major funding figures
| Figure or initiative | What it means | What it does not mean |
|---|---|---|
| About €500 million | The Commission says Europe has invested approximately this amount in open RISC-V through the Chips Joint Undertaking. | It should not be treated as an independently itemised, audited RISC-V-only budget without further breakdown. |
| €20–40 billion | The Commission’s estimated investment range for the proposed advanced-chip pilot and associated ecosystem. | It is not money already spent on RISC-V. |
| €3–4 billion | The Commission’s estimate for potential mobilisation for European fabless chip-design companies. | It is not a guaranteed allocation or completed investment. |
| €40 million and €50 million | Indicative EU budgets listed for different 2026 Chips JU calls. | They are broad calls and not necessarily dedicated RISC-V programmes. |
What success should look like
Announcements and prototypes are useful early indicators, but they are not sufficient evidence of sovereignty. A serious assessment should ask:
- Are European companies producing usable processor IP and complete SoCs?
- Are publicly funded designs repeatedly reaching silicon?
- Can projects access European pilot lines or foundries at commercially useful process nodes?
- Do the chips support Linux, virtualization, compilers, drivers, and real target workloads?
- Are automakers, cloud providers, telecom operators, industrial firms, and defence customers buying them?
- Can companies survive after public grants expire?
- Are packaging, testing, memory, substrates, and critical equipment available?
- Can customers inspect, verify, update, and maintain the technology?
- Do different RISC-V implementations provide a predictable software base despite optional extensions?
- Will public procurement create enough demand to establish production scale?
By 2030, the strongest evidence would be deployed products, recurring customers, mature toolchains, repeatable manufacturing, and companies with sustainable revenue—not simply a larger number of funded projects.
The bottom line
The EU’s RISC-V strategy is credible, but its objective is selective technological autonomy rather than complete semiconductor autarky.
RISC-V can reduce dependence on proprietary processor licensing and give European companies more freedom to design, customise, audit, and maintain processors. The eProcessor project, EPI, Codasip, Openchip, Chips JU infrastructure, and the proposed Chips Act 2.0 all point toward a deeper European design ecosystem.
Yet a RISC-V processor is only one component of a modern chip platform. Europe must still solve manufacturing access, EDA dependence, packaging, software support, security assurance, supply-chain resilience, customer adoption, and production economics.
The most accurate description is therefore: Europe is using RISC-V as one building block of chip sovereignty—not as a shortcut to a fully independent chip supply chain.
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