There is no universal winner. Choose the foundry that can qualify your specific design at the required performance, power, area, yield, schedule, package, geography and lifecycle cost. A label such as “2nm” is not a common measuring stick: node names do not establish comparable transistor density, power, price, yield or availability. Start with a process candidate and a written specification, then obtain comparable proposals and production evidence from TSMC, Samsung Foundry and Intel Foundry.
The practical decision is a risk-adjusted manufacturing program, not a logo comparison. TSMC is the most extensively documented pure-play scale option; Samsung combines leading-edge logic with a broad specialty portfolio and Multi Project Wafer (MPW) prototyping; Intel combines wafer fabrication with advanced packaging and assembly/test, while its newest external-foundry roadmap still requires careful milestone and demand diligence.
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What you are actually choosing
A foundry choice determines far more than where wafers are etched. It affects the process design kit (PDK), standard-cell and memory libraries, analog and radio-frequency options, intellectual-property (IP) blocks, mask and non-recurring-engineering charges, yield learning, packaging, test, logistics and the ability to obtain wafers throughout the product life.
Compare like with like: the same die size, clock target, voltage range, memory configuration, package, annual volume and qualification standard on a named process revision. Ask each vendor to identify whether a date is development, risk production, customer tape-out, qualification or high-volume manufacturing (HVM). A public roadmap is a plan, not a capacity reservation or a guarantee for your design.
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At-a-glance comparison
| Decision factor | TSMC | Samsung Foundry | Intel Foundry |
|---|---|---|---|
| Business model | Pure-play foundry; it says it does not design, manufacture or market semiconductor products under its own name. | Integrated manufacturing network offering leading-edge logic, specialty processes and packaging services. | Intel’s own product manufacturing plus external foundry, packaging and test services. |
| Public scale or status | TSMC reported 12,682 products for 534 customers using 305 technologies in 2025, with more than 17 million 12-inch-equivalent wafers of annual capacity. | Public pages describe a portfolio from 180nm to 2nm and beyond; comparable customer, capacity and yield figures are not stated. | Intel’s 2025 Form 10-K says 18A entered HVM in late 2025 for its first Core Ultra Series 3 processor; 14A is in active development and seeking external customers. |
| Leading-edge information | N2 volume production began in the fourth quarter of 2025; N2P is scheduled for the second half of 2026. | Samsung describes a 2nm-and-beyond roadmap, but the public material does not establish a comparable production date or yield. | 18A uses RibbonFET and PowerVia; 14A milestones and external demand are explicit execution risks in Intel’s filing. |
| Specialty and prototyping | Broad technology menu and 3DFabric packaging; exact specialty choices depend on the design. | Embedded non-volatile memory, RF, CMOS image sensor, high-voltage and BCD options; MPW services can share mask and wafer costs for prototypes. | Intel 3 and Intel 16 are listed alongside 18A; packaging and test are part of the offering. |
| Advanced packaging | 3DFabric family of stacking and advanced-packaging solutions. | Advanced heterogeneous integration and turnkey packaging are listed in its manufacturing portfolio. | 2D, 2.5D and 3D interconnects, including EMIB and Foveros, plus assembly and test. |
| Public price comparison | Not stated in comparable public evidence. Obtain design-specific wafer, mask, NRE, package, test and commitment quotes. | ||
Sources: TSMC 2025 Annual Report, TSMC technology page, Samsung process technology, Samsung manufacturing, Intel manufacturing and Intel 2025 Form 10-K.
TSMC: the scale and ecosystem benchmark
What the public record supports
TSMC describes itself as a pure-play foundry: customers bring designs, while TSMC manufactures them without selling a competing chip under its own brand. Its 2025 annual report records 534 customers, 12,682 products and 305 distinct technologies. Annual capacity exceeded 17 million 12-inch-equivalent wafers in 2025, and 74% of wafer revenue came from 7nm-and-smaller processes. Those are company-reported aggregate measures, not an allocation promise for a new customer or a particular node.
Manufacturing and subsidiaries span Taiwan, Nanjing, Arizona and Japan. TSMC says construction of a specialty-technology fab in Dresden began in 2024. Its Japan Advanced Semiconductor Manufacturing (JASM) first Kumamoto facility entered volume production at the end of 2024, and a second facility began construction in 2025. Ask which legal entity and physical site would actually run your wafers; the corporate footprint does not mean every process is available at every location.
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TSMC states that N2 volume production started in the fourth quarter of 2025 and describes first-generation nanosheet transistors. The same technology material schedules N2P volume production for the second half of 2026. Treat the N2 statement as a dated production-status claim and N2P as a plan. For a tape-out, request the PDK revision, approved IP list, design-rule maturity, qualification data, risk-production terms and the date at which your exact variant can receive committed starts.
Packaging fit
TSMC’s 3DFabric family covers stacking and advanced packaging. A chiplet or high-bandwidth-memory design should be quoted as one flow: front-end wafer, interposer or substrate, assembly, thermal solution, known-good-die handling and final test. Confirm ownership of each step, package warpage limits, electrical and thermal models, and the recovery path if an assembly site is constrained.
Samsung Foundry: breadth, specialty options and MPW access
Process portfolio
Samsung lists logic processes from 180nm to 2nm and beyond. Its specialty menu includes embedded non-volatile memory, RF, CMOS image sensors, high voltage and BCD. That breadth can be decisive when one product combines digital logic with power management, sensors, connectivity or embedded memory. Samsung’s performance, power and scalability descriptions are vendor claims; require design-specific projections and independent qualification evidence before assigning a business case.
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Manufacturing network and prototyping
Samsung presents integrated U.S. and Korean sites as a multi-continent network. Its MPW service lets several designs share wafer and mask costs, which can lower the cost of an early silicon experiment. MPW is not automatically a production path. Ask whether the MPW shuttle uses the same process revision, libraries, design rules, package assembly and reliability screens planned for volume. Establish how a prototype moves into dedicated wafers, who owns yield learning and which changes trigger a new qualification.
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- What comparable yield and cycle-time data apply to your die size and package?
- Which fab and backup site are assigned to the named process?
- What capacity can be contractually reserved during ramp?
- Which third-party IP, memory compilers and EDA flows are qualified on the exact revision?
Samsung’s manufacturing description is available at semiconductor.samsung.com/foundry/manufacturing/, and its process portfolio at semiconductor.samsung.com/foundry/process-technology/.
Intel Foundry: integrated fabrication, packaging and a milestone-dependent roadmap
18A production evidence
Intel’s 2025 Form 10-K says Intel 18A entered high-volume manufacturing in late 2025, uses RibbonFET and PowerVia, and is used in the company’s first Core Ultra Series 3 processor. That establishes an internal product and production milestone. It does not, by itself, prove that an external customer’s design is qualified, shipping at volume or receiving the same yield and delivery performance.
14A and external-customer risk
Intel describes 14A as in active development and says it is seeking external customers. The filing warns that without significant external demand and achievement of milestones, Intel may pause or discontinue 14A and later leading-edge development. A buyer considering 14A should tie engineering payments, mask release, capacity reservations and redesign obligations to measurable PDK, yield, qualification and customer milestones. Include termination and migration rights if a roadmap checkpoint is missed.
Packaging and ecosystem
Intel’s manufacturing page lists Intel 18A, Intel 3 and Intel 16, along with 2D, 2.5D and 3D packaging and assembly/test. EMIB bridge technology and Foveros stacking can be relevant for chiplets, but the decision depends on the exact package, substrate, thermal envelope and known-good-die flow. Intel’s April 29, 2025 Foundry Direct Connect announcement named Synopsys, Cadence, Siemens EDA and PDF Solutions among ecosystem participants and included executives from MediaTek, Microsoft and Qualcomm. Those names demonstrate engagement, not a guarantee that a particular IP block or flow is qualified for your design. The announcement quotes Intel CEO Lip-Bu Tan: “Our No. 1 job is to listen to our customers and earn their trust by creating solutions to enable their success.” This is a stated priority, not evidence of comparative customer satisfaction.
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Read the manufacturing overview at intel.com/content/www/us/en/foundry/manufacturing.html, the 10-K at sec.gov/Archives/edgar/data/50863/000005086326000011/intc-20251227.htm and the April 2025 announcement at intel.com/content/www/us/en/newsroom/news/corporate/intel-foundry-gathers-customers-partners-outlines-priorities.html.
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Compare the process, not the node number
Build one request-for-information (RFI) template and send it unchanged to each candidate. Require a named process revision and a date for every answer.
- PPA: Request modeled performance, power and area at your operating corners, including SRAM, I/O, analog and memory macros.
- Design enablement: Check PDK maturity, design rules, extraction decks, sign-off tools, standard cells, memory compilers, interface IP and supported EDA versions.
- Yield and reliability: Ask for comparable die-size and complexity data under nondisclosure, infant-mortality and lifetime reliability results, defect-density assumptions and the yield-learning plan.
- Change control: Define how process, IP, mask or package changes are notified, evaluated and requalified.
- Lifecycle: Establish production-life commitments, last-time-buy rules, obsolescence notice, automotive or industrial qualification and a second-source strategy.
Do not substitute a vendor’s marketing graph for these deliverables. A smaller advertised node can lose on total system cost if it needs larger dies, more masks, scarce IP or a package that your supply chain cannot qualify.
Model total cost and schedule
Public material does not provide comparable wafer prices for the three foundries. Build a cost model that separates one-time and recurring items:
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| Cost or commitment | What to request |
|---|---|
| Mask set and NRE | Itemized mask, shuttle, engineering, characterization and re-spin charges, with payment milestones. |
| Wafer price | Price by process revision, wafer diameter, volume band and committed term; state whether test wafers are included. |
| Yield assumption | Ramp curve, usable-die calculation, scrap treatment and who bears the cost of an agreed yield shortfall. |
| Package and test | Assembly, substrate or interposer, burn-in, final test, known-good-die and thermal/mechanical qualification charges. |
| Capacity reservation | Minimum starts, take-or-pay terms, allocation priority, lead time, cycle time and remedies for missed milestones. |
| Migration cost | Porting effort, new masks, IP relicensing, requalification and inventory write-offs if the process or site changes. |
Use an expected-cost view: a lower quoted wafer price can be outweighed by a late tape-out, a lower first-pass yield, an unavailable package or a redesign forced by an immature IP block. Keep optimistic, base and downside schedules, and obtain written assumptions for each.
Packaging, test and system integration
For chiplets, stacked memory or high-power devices, packaging can dominate electrical performance and cost. Compare:
- Interposer, bridge or direct-bonding capability and the maximum die count.
- Substrate availability, line/space limits, warpage control and thermal design rules.
- Assembly location, test ownership, burn-in capacity and traceability.
- Known-good-die criteria and how failed tiles are handled.
- High-bandwidth-memory, optical or high-speed I/O qualification where applicable.
- Whether package models, mechanical drawings and thermal data arrive early enough for system design.
TSMC’s 3DFabric, Samsung’s heterogeneous-integration and turnkey-packaging offerings, and Intel’s 2D, 2.5D and 3D portfolio are not interchangeable labels. Compare the complete bill of materials, qualification plan and hand-off between wafer, assembly and test sites.
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Geography, resilience and control
Identify the actual fab and assembly/test sites in your proposal. Evaluate export controls, customs, shipping lanes, local incentives, power and water resilience, earthquake or weather exposure, disaster recovery and the legal jurisdiction governing the contract. A multi-continent network can improve resilience only if your process, package and backup capacity are genuinely qualified there.
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A step-by-step foundry selection process
- Freeze the product specification. Document throughput, latency, power, die area, interfaces, memory, operating corners, package, annual volume, qualification grade and target launch date.
- Create a shortlist of process candidates. Select named TSMC, Samsung or Intel variants that support the required IP and package; do not shortlist by “2nm” or “3nm” alone.
- Run an enablement audit. Verify PDK release, design-rule stability, sign-off decks, libraries, memory, interface IP, EDA versions and design-service support.
- Request comparable modeling. Give every vendor the same netlist assumptions and ask for PPA, die-size, yield and schedule ranges with stated confidence levels.
- Prove the package path. Review substrate, interposer or bridge, thermal, assembly, test and known-good-die flows before committing to front-end wafers.
- Audit production evidence. Separate internal HVM, customer tape-outs, qualification and external shipments. Request confidential yield, reliability and cycle-time evidence for similar products.
- Negotiate capacity and remedies. Specify starts, ramp dates, allocation priority, lead times, change notices, delay remedies and the right to move work if milestones fail.
- Run a prototype or shuttle when appropriate. An MPW can reduce early mask and wafer cost, but confirm that its process and qualification path match production.
- Score the downside case. Quantify redesign, inventory, schedule slip, package failure and geopolitical exposure; weight these risks against nominal wafer economics.
- Approve with stage gates. Make PDK maturity, tape-out, first silicon, yield, reliability, package qualification and volume release separate go/no-go decisions.
Which choice fits common situations?
High-volume leading-edge consumer or compute silicon
TSMC’s documented scale and broad customer base may reduce ecosystem and capacity uncertainty, but you still need a node-specific allocation and yield commitment. Samsung can be competitive when its exact process offers the required IP, power target or package. Intel 18A is a credible production option for designs that fit its qualified flow; external buyers evaluating 14A should make roadmap milestones and fallback rights central to the contract.
Prototype, mixed-signal or specialty product
Samsung’s specialty portfolio and MPW service may simplify an early mixed design or lower the cost of a shared prototype. TSMC and Intel may also fit, depending on analog, RF, embedded-memory, I/O and lifecycle requirements. Select the process that avoids unnecessary leading-edge cost and has proven macros for the product.
Chiplet or vertically integrated system
Evaluate packaging first. Intel’s EMIB and Foveros, TSMC’s 3DFabric and Samsung’s heterogeneous-integration services each require a design-specific review of interconnect, thermal, substrate, assembly and test. A foundry that cannot provide the whole qualified flow can leave you coordinating multiple vendors and absorbing interface risk.
Geographic diversification requirement
Map the exact process and package to the sites that can run them. TSMC reports facilities and subsidiaries in Taiwan, Nanjing, Arizona and Japan and a Dresden specialty-fab project; Samsung describes U.S. and Korean sites; Intel describes worldwide wafer, assembly and test locations. Site count alone is not redundancy unless the same design is qualified and capacity is contractually available at the alternate location.
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Contract and diligence checklist
- Named process revision, fab, package and test site.
- PDK, IP and EDA support dates tied to tape-out and production milestones.
- Wafer, mask, NRE, package and test pricing with yield assumptions.
- Capacity reservation, minimum commitments, lead times and allocation rules.
- Yield, reliability, change-control and requalification obligations.
- Export-control, data-security, confidentiality and audit provisions.
- Disaster recovery, alternate-site qualification and logistics responsibilities.
- Lifecycle, last-time-buy, obsolescence notice and second-source plan.
- Termination, redesign funding and migration rights if a roadmap milestone fails.
Bottom line: choose the lowest total risk for your exact chip
Use TSMC when its specific process, IP and package deliver the best combination of proven scale, schedule and ecosystem support. Consider Samsung when specialty integration, MPW prototyping or a particular logic roadmap solves a requirement the others do not. Consider Intel when its qualified process and integrated packaging/test flow improve system economics, while treating 14A and later external-roadmap commitments as milestone-dependent until your program has contractual evidence.
The winning proposal is the one that survives technical, financial and supply-chain diligence: a named process with usable IP, measured yield evidence, a qualified package, committed capacity, transparent change control and a credible fallback. Obtain those facts before comparing node labels or signing a wafer commitment.
Frequently Asked Questions
Are TSMC, Samsung and Intel node names directly comparable?
No. A label such as 2nm does not establish equivalent transistor density, performance, power, yield, price or availability. Compare design-specific PPA, rules, IP and qualification data on named process revisions.
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No. Intel’s 2025 Form 10-K records 18A HVM for an internal Core Ultra Series 3 processor. An external customer still needs its own PDK, IP, yield, reliability, package and delivery qualification.
Can Samsung MPW wafers be used as production qualification?
Not automatically. Confirm that the MPW process revision, libraries, package and reliability screens match the planned production flow, and define how prototype results transfer to dedicated wafers.
What should a foundry quote include?
Request itemized masks and NRE, wafer price by volume, yield assumptions, package and test charges, capacity reservations, lead times, minimum commitments, change-control terms and migration remedies. Comparable public prices are not available.
How should chiplet projects compare foundries?
Evaluate wafer, interposer or bridge, substrate, stacking, thermal design, assembly, test and known-good-die handling as one qualified flow. Packaging capability can outweigh a nominal front-end node advantage.
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