ASML’s extreme ultraviolet (EUV) machines print the most demanding layers of advanced chips by turning laser-hit tin droplets into 13.5-nanometer light, steering that light with multilayer mirrors in a vacuum, and projecting a reticle pattern onto a silicon wafer. Chipmakers depend on the technology because its short wavelength can print some intricate layers in fewer exposures than deep ultraviolet (DUV) methods, improving the manufacturability of leading-edge logic and memory. EUV is not used for every layer or every chip, and DUV remains essential.
What EUV lithography is
Lithography is the patterning stage of semiconductor manufacturing. A scanner projects a mask pattern onto photoresist coated on a wafer; later steps such as etching and deposition convert that patterned resist into transistors, contacts and interconnects. The scanner does not make a finished chip by itself. It repeatedly prints selected layers as the wafer moves through the broader fab process.
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EUV means extreme ultraviolet. ASML’s systems use light at a wavelength of 13.5 nanometers—far shorter than the wavelengths used by conventional DUV scanners. ASML describes this wavelength as nearly in the X-ray range. Shorter wavelength generally allows a projection system to resolve smaller, more closely spaced features, provided the optics, resist, masks and process controls can support them.
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How an ASML EUV machine creates and prints the pattern
1. Tin droplets become a plasma light source
The light starts with a stream of microscopic molten-tin droplets. A low-intensity laser pulse first flattens each droplet. A much stronger carbon-dioxide laser pulse then strikes the flattened tin, vaporizing it into a hot plasma that emits EUV radiation.
ASML’s 2025 annual-report story says its latest commercial sources repeat this tin-plasma process 60,000 times per second. ASML’s product overview separately describes the source as operating at up to 50,000 repetitions per second. Those figures refer to different descriptions; neither should be treated as a universal operating rate for every EUV machine.
2. Vacuum replaces ordinary air and lenses
At 13.5 nm, air absorbs EUV light, as do nearly all ordinary optical materials. A beam that traveled through a normal lens barrel would lose its energy before reaching the wafer. ASML therefore places the source, optical path and wafer exposure area in high vacuum.
Because refractive lenses cannot do the job, the machine uses mirrors. The mirrors were developed with ZEISS and use more than 100 carefully engineered material layers, according to ASML. Each layer contributes to reflecting the narrow EUV band efficiently. The mirrors must also maintain their shape and alignment to extraordinary tolerances: small errors can blur or shift features across the wafer.
3. A reflective reticle carries the chip pattern
In a DUV scanner, a mask can transmit light through transparent regions. An EUV reticle instead works as a multilayer reflector. The pattern is encoded in the reticle’s reflective and absorbing areas, and the scanner illuminates it with EUV light inside the vacuum environment.
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4. The projection optics shrink the image
Reflected light from the reticle enters the optical column and is directed toward the wafer by a sequence of mirrors. The projection system reduces the reticle image by a factor of four before printing it onto the wafer. Reduction lets the reticle hold a larger, more manageable pattern while the wafer receives the scaled version.
5. The wafer enters through an air lock and is positioned
Wafers cannot simply be carried from room air into the exposure chamber without disturbing the vacuum. ASML describes wafer transfer through an air lock. Its product information also lists positioning accuracy of 25 micrometers for the wafer-handling system. That mechanical positioning is separate from the nanometer-scale imaging requirements inside the projection optics, but both are necessary for overlaying one layer accurately on the layers already printed.
6. Photoresist records the projected image
The EUV image exposes the wafer’s photoresist. After exposure, the wafer is developed so that selected regions remain or are removed, depending on the resist chemistry. Etching, deposition, implantation and cleaning then build the device structures. The scanner’s contribution is the controlled transfer of a geometric pattern; it does not perform those subsequent fabrication operations.
Why 13.5 nm light can reduce multi-patterning
DUV scanners remain highly capable and are used throughout a modern fab. However, when a target layer contains features too dense or complex for one DUV exposure, manufacturers can use multi-patterning. They divide the desired layout into simpler masks, expose the wafer multiple times and combine the results through additional process steps.
Each extra patterning pass can add masks, alignment work, deposition or etch steps, inspection opportunities and cycle time. It can also create more chances for defects or overlay errors. EUV’s shorter wavelength and imaging capability can allow certain critical layers to move from multiple patterning to a single EUV patterning step. ASML says that simplification can improve productivity, defects, cost and cycle time, although the outcome depends on the customer’s design and process integration.
EUV therefore does not “replace” DUV. A leading-edge chip may use EUV for its most difficult layers while DUV handles less demanding layers, cut lines, peripheral structures and many mature-node products. The economic value comes from using EUV where its capability offsets enough extra process complexity to justify the machine and integration cost.
NXE and EXE: the two EUV system generations
| System family | Numerical aperture | ASML-stated resolution | Role and production context |
|---|---|---|---|
| NXE standard EUV | 0.33 NA | 13 nm | High-volume production for advanced logic and memory; critical layers associated with 7 nm, 5 nm and 3 nm logic generations |
| EXE High-NA EUV | 0.55 NA | 8 nm | Designed for future advanced logic and memory nodes; ASML describes high-volume-manufacturing support in its 2025–2026 roadmap |
Numerical aperture (NA) describes how much angular information the projection optics can collect. Increasing NA generally improves resolution, which is why EXE’s 0.55 NA is aimed at smaller features than NXE’s 0.33 NA. Higher NA also creates design trade-offs, including a larger and more demanding optical system and tighter requirements for masks, focus control and process integration.
ASML says it shipped the first High-NA system modules to Intel in December 2023. Its stated 2025–2026 high-volume-manufacturing timeline is a company roadmap, not an independently confirmed industry-wide deployment date. Early module shipments, pilot work and broad production adoption are different milestones.
Why chipmakers depend on EUV—and on ASML
It addresses the hardest layers
Modern logic and memory designs contain layers where line width, spacing and overlay margins are especially difficult. EUV gives process engineers another way to print those layers without stacking as many DUV exposures. That can make a design feasible at a targeted density or make an existing process less cumbersome.
It can lower the number of process steps
Fewer patterning passes can mean fewer masks, fewer wafer moves and fewer opportunities for alignment and defect problems. The benefit is not automatic: a customer must evaluate the complete process, including resist behavior, etch transfer, inspection and yield. Still, reducing multi-patterning on the right layers is a central reason EUV is valuable in high-volume manufacturing.
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The equipment is unusually specialized
ASML’s 2025 Annual Report calls the company the only manufacturer of EUV lithography systems. That sole-supplier position reflects the machine’s combination of a high-power tin-plasma source, vacuum engineering, multilayer mirrors, reflective reticles, precision stages, control software and service infrastructure. A chipmaker cannot substitute a conventional optical scanner simply by installing a different lens.
ASML reported 48 EUV system sales out of 535 total system sales in 2025. The comparison shows that EUV is a specialized subset of ASML’s wider lithography, metrology and inspection business. It does not mean that every chipmaker owns an EUV tool, that every advanced chip uses EUV, or that EUV represents most of the company’s unit sales.
Productivity matters as much as resolution
A scanner is valuable only when it can expose wafers reliably at production scale. Buyers therefore compare more than the smallest printable feature. They examine throughput, uptime, overlay, defect performance, the number of exposures required for a layer, integration with the fab’s track and inspection systems, and the cost per wafer. A higher-resolution system that cannot meet production requirements would not solve the manufacturer’s problem.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the major EUV numbers mean
13.5 nm wavelength
This is the central optical property of the source, not the size of every transistor or wire. The wavelength helps determine imaging capability, while NA, illumination, resist chemistry, mask effects and process control determine what can actually be printed.
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These are the NA values ASML lists for NXE and EXE, respectively. The larger EXE value supports finer imaging but brings optical and process trade-offs. NA alone does not tell you a chip’s final density or performance.
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13 nm and 8 nm stated resolution
These are ASML’s stated resolutions for the NXE and EXE platforms on its product information. Resolution is a system capability under specified imaging conditions, not a guarantee that every layer, design rule or production result will match that number.
60,000 source repetitions per second
ASML associates this figure with the latest commercial tin-plasma sources in its 2025 annual-report story. It describes how often the source-generation sequence can repeat; it is not a wafer-throughput figure and should not be read as the number of wafers exposed per second.
1,000 watts of EUV source power
ASML reported a 1,000-watt EUV light-source demonstration in April 2025. That was a demonstrated source milestone, not a claim that all installed production machines deliver 1,000 watts or that source power alone determines wafer throughput.
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- “EUV prints the whole chip.” It prints selected lithography layers. Etch, deposition, implantation, cleaning, inspection and packaging remain separate operations.
- “EUV makes DUV obsolete.” DUV continues to pattern many layers and remains broadly used across advanced and mature processes.
- “A 3 nm node means every feature is 3 nm.” Node names describe technology generations and are not literal measurements of every printed dimension.
- “More source power automatically means more output.” Throughput also depends on resist dose, optics, stage motion, uptime, mask behavior and the rest of the fab integration.
- “Any advanced chip must use EUV.” EUV adoption varies by design, process generation, manufacturer and layer. Some products can use DUV multi-patterning or other approaches for particular patterns.
How to evaluate an EUV claim
- Check whether the statement refers to NXE standard EUV or EXE High-NA EUV.
- Separate wavelength, NA and stated resolution from actual production throughput and yield.
- Ask which layer or pattern is being discussed; EUV benefits are layer-specific.
- Look for the measurement date and the source of the number. ASML’s product pages and 2025 Annual Report provide the figures cited here, while product specifications and roadmaps can change.
- Distinguish a laboratory or source demonstration from installed-fleet performance and from high-volume manufacturing.
The bottom line for the semiconductor industry
EUV works by repeatedly converting tin droplets into plasma, collecting 13.5 nm radiation with multilayer mirrors, transporting it through a vacuum, shrinking a reflective-reticle image fourfold and exposing photoresist on a precisely positioned wafer. Chipmakers depend on it because the combination of short wavelength and high-precision imaging can simplify selected critical layers that would otherwise require multiple DUV patterning steps. The dependence is strategic rather than universal: EUV is a specialized tool for the most demanding production layers, while DUV and the rest of the semiconductor process remain indispensable.
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