AI accelerators were the semiconductor industry’s main growth engine in 2025, but the bigger story was a shift from transistor scaling to whole-system engineering. High-bandwidth memory, advanced packaging, networking, power delivery, chiplets, software, manufacturing capacity, and supply-chain resilience became just as important as the process node used to build a chip.
That distinction matters for investors, technology executives, procurement teams, and students. A strong AI-chip market did not mean every semiconductor segment was growing equally. Instead, demand concentrated around the infrastructure needed to train and run AI while automotive, industrial, consumer, and communications markets recovered at different speeds.
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What actually happened to semiconductors in 2025?
Early forecasts and later results should not be confused. In October 2024, Gartner forecast 14% semiconductor-revenue growth for 2025. Its preliminary result, published in January 2026, put worldwide semiconductor revenue at $793 billion, up 21% year over year.
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The six most important trends were therefore interconnected:
- AI accelerators became the principal growth engine.
- HBM and advanced packaging became strategic bottlenecks.
- AI computing spread into PCs, smartphones, vehicles, and edge devices.
- Chiplets, backside power, new transistor architectures, and AI-assisted design changed how chips were built.
- Governments and manufacturers pursued more geographically resilient supply chains.
- Power efficiency, mature-node capacity, and application-specific silicon became first-order business issues.
1. AI accelerators became the industry’s growth engine
Training and running modern AI models requires enormous amounts of parallel computation, memory bandwidth, and data movement. That makes a conventional CPU alone inefficient for many workloads. GPUs became the dominant platform for large-scale training and much inference because they can perform many similar mathematical operations simultaneously and are supported by mature software ecosystems.
The market is broader than GPUs, however. A modern AI system can include:
- CPUs for general-purpose operating-system and application work.
- GPUs for highly parallel graphics and AI workloads.
- NPUs for efficient neural-network operations on local devices.
- TPUs and similar domain-specific processors designed around particular AI workloads.
- DPUs for networking, storage, and infrastructure processing in data centers.
- Custom ASICs designed for a specific customer or application.
Hyperscalers are developing custom silicon because a purpose-built chip can reduce operating cost and power use when deployed at very large scale. The trade-off is substantial upfront engineering expense and less flexibility if models or workloads change. General-purpose accelerators remain valuable when customers need a broad software ecosystem or want to support rapidly changing AI applications.
The economic effect extends well beyond accelerator designers. AI infrastructure also increases demand for HBM, networking chips, optical interconnects, substrates, advanced testing, power-management devices, high-speed storage, semiconductor equipment, and cooling systems. Deloitte estimated that generative-AI chips exceeded $125 billion in 2024 and represented more than 20% of total chip sales; that is Deloitte’s estimate, not a universal industry measurement.
For investors, the important lesson is that “AI exposure” can mean different things. A company may benefit from AI through compute, memory, packaging, manufacturing, networking, or power infrastructure rather than by selling an accelerator itself.
2. HBM and advanced packaging became strategic bottlenecks
Building more accelerator wafers does not automatically produce more complete AI systems. The processor must be connected to enough memory, mounted in a suitable package, tested, powered, and cooled.
High-bandwidth memory, or HBM, stacks memory dies vertically and connects them to an accelerator through a wide interface. This provides much more bandwidth than conventional system memory, which is critical when AI processors would otherwise sit idle waiting for data.
Advanced packaging brings compute dies, HBM stacks, interposers, substrates, and sometimes networking components together. Important approaches include:
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- 2.5D packaging: multiple dies sit side by side on an interposer that provides dense connections.
- 3D stacking: dies are placed vertically to shorten connections and increase density.
- Chiplet packaging: separate functional dies are combined into one system rather than placing everything on one monolithic die.
- Hybrid bonding and die stacking: techniques that create very dense vertical connections.
TSMC identifies CoWoS, InFO, SoIC, and silicon-photonics-related technologies as parts of its advanced-packaging strategy. It also reported that it was developing larger CoWoS interposers for AI and high-performance computing requirements, with volume production planned for 2026.
Deloitte cited analyst estimates that TSMC’s CoWoS capacity could increase from approximately 35,000 wafers per month in 2024 to 70,000 and eventually 90,000 by the end of 2026. Those are estimates cited by Deloitte, not confirmed TSMC capacity guidance.
Micron announced HBM3E products and SOCAMM memory solutions for AI-server platforms in March 2025. Micron described HBM as foundational to high-performance AI systems and said its HBM3E was being used in NVIDIA Hopper and Blackwell systems; those are company claims.
Packaging is no longer merely a back-end manufacturing detail. It affects bandwidth, latency, heat removal, defect rates, testing, yield, and cost. A useful analogy is that transistor scaling improves individual buildings, while packaging improves the roads, bridges, utilities, and transit system connecting the entire city.
The trade-off is complexity. More advanced packages require specialized substrates and interposers, more difficult thermal management, known-good-die testing, and scarce capacity. A successful accelerator design can still be constrained if the industry cannot package it at the required scale.
3. AI moved into PCs, phones, cars, and edge devices
AI computing increasingly followed a distributed model:
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- Cloud data centers: large-model training and the most demanding inference.
- Enterprise edge systems: local inference for factories, offices, retail, and other controlled environments.
- PCs and smartphones: transcription, translation, image enhancement, assistants, and selected generative features.
- Automobiles: driver assistance, sensor fusion, cockpit systems, and autonomy-related workloads.
- Industrial and IoT devices: machine vision, predictive maintenance, and local control.
An AI PC is not simply a computer with an AI label. It generally includes an NPU that handles supported neural-network operations more efficiently than a CPU. The CPU remains responsible for general-purpose tasks, while the GPU handles graphics and highly parallel workloads. The NPU is an additional processor for selected AI functions.
Local processing can reduce latency, preserve privacy, work without a reliable internet connection, and lower cloud-transfer costs. Cloud processing still offers larger models, centralized updates, and more available computing power. The likely long-term model is hybrid: some work runs locally, while more demanding tasks move to the cloud.
The presence of an NPU does not guarantee useful on-device AI. Benefits depend on software support, model availability, local memory, developer adoption, model compression, and whether users actually use the features. This is why “AI PC shipments” and meaningful AI adoption are not interchangeable measures.
Deloitte identified lightweight generative-AI accelerators for PCs, smartphones, and enterprise-edge systems as a major 2025 trend. TSMC likewise described AI demand spreading across data centers, PCs, smartphones, automobiles, and IoT devices. Those company and industry outlooks show direction, but they do not prove that every category had reached mass adoption during 2025.
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Moore’s Law did not simply stop; the industry changed how it pursued progress. Designers combined smaller transistors with specialized architectures, multiple dies, new power-delivery methods, and better automation.
Chiplets
Chiplets separate a complex processor into smaller dies that can be combined in one package. This can allow a designer to:
- Mix different process nodes in the same product.
- Reuse proven input/output, cache, or accelerator blocks.
- Improve yield by manufacturing smaller dies.
- Customize products for different customers.
- Avoid putting every function on the most expensive leading-edge node.
Chiplets are not a universal solution. Die-to-die standards, interoperability, thermal design, security, known-good-die testing, software validation, and substrate capacity all create new challenges. Connections between dies can also introduce latency or consume more energy than connections inside a monolithic die.
Gate-all-around transistors and backside power
New transistor structures aim to improve control over current flow as dimensions shrink. Backside power delivery moves some power connections to the rear of the wafer, potentially reducing congestion on the signal side and improving power delivery.
Intel describes its 18A process as combining RibbonFET gate-all-around transistors with PowerVia backside power delivery. Intel reported that 18A entered production in 2025. Production entry should not be confused with broad commercial availability, high-volume customer adoption, or independently verified performance.
TSMC reported that 74% of its 2025 wafer revenue came from 7-nanometer-and-more-advanced technologies. It also scheduled A14 volume production for 2028. That is a company roadmap, and future schedules can change.
Process labels such as “3 nm,” “2 nm,” and “18A” are not directly comparable across manufacturers. Density, power, performance, design rules, yield, packaging, and actual availability are more useful measures than the name alone.
AI-assisted chip design
AI and automation increasingly help design teams explore layouts, identify problems earlier, improve verification, and automate repetitive tasks. Deloitte described this as a “shift-left” approach: finding errors earlier in the design cycle when they are less expensive to fix.
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5. Governments pursued resilient, not fully independent, supply chains
Semiconductor production depends on a globally distributed network of electronic-design-automation software, intellectual property, lithography and other equipment, wafer fabrication, memory, packaging, substrates, chemicals, gases, testing, maintenance, and specialist labor.
Governments therefore pursued domestic capacity in selected strategic areas, including leading-edge logic, advanced packaging, memory, power semiconductors, and defense-related supply. The objective was generally resilience and assured access—not complete national self-sufficiency.
The Semiconductor Industry Association’s 2025 U.S. industry report connected semiconductor research and manufacturing with AI infrastructure and national competitiveness. TSMC reported plans to expand its U.S. footprint with additional fabs, advanced-packaging facilities, and an R&D center while continuing major investment in Taiwan.
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That illustrates the likely model: geographic diversification without abandoning the Taiwan-centered ecosystem that already contains deep manufacturing expertise, suppliers, infrastructure, and customer relationships.
Localization can improve resilience, political control, defense assurance, and customer confidence. It can also raise construction and operating costs, duplicate capacity, lengthen qualification timelines, and leave fabs dependent on imported equipment, materials, intellectual property, packaging inputs, or skilled labor.
A domestic fab is therefore not the same thing as a domestic supply chain. A plant located in the United States or Europe may still rely on suppliers across Asia, the Netherlands, Japan, South Korea, Taiwan, and elsewhere.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.6. Power efficiency and mature-node capacity became decisive
AI systems are increasingly limited by electricity, cooling, rack density, and data movement—not only by available compute. The best chip is not necessarily the one with the highest benchmark score. It may be the one that delivers adequate performance within a data center’s power, thermal, and infrastructure budget.
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- Power-management ICs and voltage regulation.
- High-voltage and high-current semiconductors.
- Silicon carbide and gallium nitride power devices.
- Efficient CPUs, accelerators, and memory systems.
- Optical and high-speed interconnects.
- Packaging that reduces data movement and improves heat removal.
- Cooling and power infrastructure around the chip.
Smaller process nodes can improve energy efficiency per operation, but total system energy can still rise when more models, users, and data centers are deployed. “Smaller” does not automatically mean lower electricity consumption for the entire computing system.
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Mature nodes remained commercially important for automotive microcontrollers, analog chips, power-management devices, sensors, display drivers, industrial controls, and connectivity components. The newest node is often unnecessary—or unsuitable—for analog, high-voltage, automotive, or industrial functions. Mature processes can be cheaper, more reliable, easier to qualify, and available in larger capacity pools.
This is another reason not to interpret semiconductor growth as a single uniform cycle. AI-exposed companies and advanced-node suppliers may experience strong demand while traditional automotive, industrial, or consumer segments remain soft.
What these trends meant for investors and business buyers
Semiconductor headlines often focus on a small group of high-profile chip designers, but the value chain is broader. A company evaluating an opportunity should examine at least three layers:
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- Demand: Are customers buying and deploying the technology, or is it mainly being announced?
- Supply: Can manufacturers produce it in volume, including memory, packaging, substrates, and testing?
- Economics: Does the performance or efficiency gain justify the chip’s engineering, equipment, power, and operating costs?
For investors, these questions help distinguish structural demand from a temporary spending surge. AI investment may remain powerful, but concentration, customer capital budgets, electricity constraints, software dependence, and changing model architectures create risks. A strong market for AI accelerators does not guarantee that every supplier, foundry, packaging provider, or equipment maker will capture equal value.
For procurement teams, the relevant comparison is usually not “fastest chip.” It is total system value: performance per watt, memory capacity and bandwidth, software compatibility, supply assurance, serviceability, lead time, and the cost of deploying the surrounding infrastructure.
Forecast versus outcome: a useful 2025 scorecard
| Expectation before 2025 | What the evidence supports |
|---|---|
| Semiconductor revenue would grow 14% in 2025. | Gartner’s preliminary January 2026 result reported 21% growth and $793 billion in revenue, so the earlier figure was a forecast, not the final reported outcome. |
| HBM revenue would reach $21 billion in 2025. | This was Gartner’s earlier forecast, up 70% from 2024. It should not be presented as measured final revenue without a later verified result. |
| AI would be the dominant chip-growth driver. | Later Gartner data showed AI semiconductors—including processors, HBM, and networking—represented nearly one-third of semiconductor sales. |
| Packaging would become a major constraint. | Expansion plans and estimates for CoWoS and other advanced-packaging capacity demonstrate that packaging was a strategic capacity issue, not merely a finishing step. |
| Domestic manufacturing would reduce supply-chain risk. | New fabs and packaging projects improve geographic resilience, but the wider ecosystem remains internationally dependent. |
Which trends are likely to persist?
The durable lesson from 2025 is that semiconductor competition is becoming a systems contest. Compute performance still matters, but so do memory bandwidth, interconnects, package yield, power delivery, cooling, software, manufacturing access, and geopolitical reliability.
AI demand is likely to remain important, but it will not erase the distinctions between data-center, edge, automotive, industrial, and consumer markets. Some workloads will stay in the cloud; others will move to local devices. Some products will need leading-edge logic; many will continue to use mature nodes. Some customers will choose general-purpose accelerators; others will accept the upfront cost of custom silicon.
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1Scan for outdated or missing drivers - takes under a minute2Repair Windows errors before they cause bigger problems3Fix the driver behind crashes, sound loss and screen glitchesThe companies best positioned for the next phase will not necessarily be those with the smallest transistor alone. They will be those that integrate compute, memory, packaging, software, power, manufacturing, and supply-chain access into a commercially viable system.
Sources: Deloitte’s 2025 semiconductor outlook; Gartner’s 2025 forecast; Gartner’s preliminary 2025 result; TSMC’s 2025 annual report; Intel’s 18A overview; Micron’s HBM3E announcement.
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