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Cadence Design Systems announced its agreement to acquire CadMOS Design Technology on January 4, 2001, and completed the purchase on March 2, 2001. CadMOS was a 25-person semiconductor software company focused on electrical signal-integrity analysis. The deal’s financial terms were not disclosed. Despite the old headline’s wording, this is a historical acquisition story—not a current Cadence product announcement.
Why Cadence wanted CadMOS
In semiconductor design, signal integrity means preserving the intended electrical behavior of signals—not cybersecurity or software integrity. As chip geometries moved into deep-submicron ranges, interactions between nearby wires and other electrical effects made noise harder to ignore. Noise could affect timing, logic behavior, yield, and confidence that a design would work as intended before it was manufactured.
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Cadence said the acquisition would strengthen signal-integrity analysis, physical-layout verification, and synthesis, place-and-route (SP&R) capabilities. It presented the technology as a way to support “correct-by-design” timing and signal-integrity closure and improve yield, performance, and predictability. Those were stated expectations, not reported post-acquisition measurements. EE Times reported the announcement and its rationale on January 4, 2001.
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What CadMOS’s tools did
CadMOS, founded in 1997 and headquartered in San Jose, offered four products, each aimed at a different kind of electrical verification.
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| Product | Role reported in 2001 |
|---|---|
| Pacific | Full-chip static-noise analysis. It examined worst-case combinations of cross-coupling, charge-sharing, propagated, and supply noise. |
| Celtic | Cell-level analysis focused on coupling-induced glitch noise in cell-based designs. |
| Arctic | Electrical rule checking; the description does not establish that it was equivalent to geometric design-rule checking. |
| Seismic | Substrate analysis. CadMOS had obtained the product through its 1999 acquisition of Apres Technologies. |
Pacific and Celtic were not interchangeable: one addressed full-chip static-noise analysis, while the other focused on cell-level glitch noise. Nor should the historical label “static-noise analyzer” be read as a claim that Pacific performed modern transient electromagnetic simulation or static timing analysis. The product descriptions and acquisition history were reported by EE Times.
How the deal fit Cadence’s existing portfolio
Cadence already had an Assura SI signal-integrity tool. In the 2001 report, Cadence executive Paul McLellan said the company considered CadMOS’s Pacific superior to its own tool and planned to replace Assura SI with Pacific and Celtic, citing their speed–accuracy trade-off and market acceptance. That is Cadence’s assessment as reported at the time, not an independently published benchmark.
The plan was to keep selling CadMOS products as a standalone verification solution while also integrating the technology into Cadence’s front-end and back-end SP&R products and its Assura physical-verification and extraction suite. CadMOS tools were commonly used after layout; Cadence also wanted to bring analysis earlier in the flow so designers could find likely risks before layout was finalized. The report projected SP&R integration probably would not occur until the second half of 2001. These were integration plans, not proof of later release dates or long-term product availability.
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Who and what were involved
CadMOS cofounder and CEO Charlie Huang had previously been vice president of R&D at Synopsys’s Epic group. Cadence said it would retain all 25 CadMOS employees, including Huang. Huang identified Texas Instruments, Lucent Technologies, Broadcom, Xilinx, AMD, and Sony among CadMOS’s customers. Dataquest analyst Gary Smith described CadMOS as a particularly strong acquisition in the EDA market; that was his opinion, not a financial valuation of the deal.
The 2001 article placed CadMOS in a competitive landscape that included Avanti, Synopsys’s Epic group, Sapphire Design Automation, Moscape, and Simplex Solutions. It noted that Snaketech products from Simplex competed with Seismic’s substrate-analysis role. These are historical names and relationships, not evidence that the same firms, brands, or products remain available today.
The announcement and the close were separate events
At announcement, Cadence expected the acquisition to close in the first quarter of 2001. EE Times subsequently reported that the transaction was completed on March 2, 2001. Its completion report said Cadence would continue standalone sales while integrating the technology into SP&R and Assura. The close confirms that Cadence bought CadMOS; it does not establish the purchase price, the products’ later roadmap, or whether the CadMOS brand persisted. EE Times reported the completion on March 2, 2001.
What the record does—and does not—show
- Established: the announcement date, completion date, CadMOS’s approximate size, its named products, and Cadence’s stated integration strategy.
- Not disclosed in the cited 2001 reporting: the acquisition price, revenue contribution, licensing economics, or measured post-deal performance.
- Not established: exact product-release milestones after the announcement, long-term survival of the CadMOS brand, or how its technology maps to current Cadence offerings.
The reports capture the strategy Cadence announced in 2001; they do not document the eventual product history. Cadence’s current portfolio spans multiple EDA categories, but its current corporate site does not by itself establish that a specific CadMOS product remains available under its original name: Cadence.
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