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Samsung Foundry has the technology and corporate assets to become a stronger competitor in advanced chipmaking, but it has not yet proved it can match TSMC’s combination of yield, customer scale and production consistency. Its prospects hinge on turning 2 nm process ramps and AI-focused design engagements into repeat, profitable production—and on combining logic, memory and advanced packaging into complete systems. As of August 16, 2026, the opportunity is credible; the outcome remains an execution question.
What Samsung Foundry does
A semiconductor foundry manufactures chips designed by other companies. Customers work with the foundry’s process technology, design rules, process-design kits (PDKs), intellectual-property blocks and manufacturing services to turn a chip design into physical wafers. Samsung established Foundry as a distinct business unit in 2017 to pursue external manufacturing customers more directly.
Samsung Foundry sits within Samsung Electronics’ Device Solutions organization, but it is not the same business as Samsung System LSI, which designs chips such as mobile processors and image sensors, or Samsung Memory, which makes DRAM, HBM and NAND. Advanced packaging is a further part of the offer: it can connect logic dies with memory and other components into a finished package. Samsung describes a portfolio spanning mature and advanced processes, including FD-SOI, FinFET generations, 3 nm gate-all-around (GAA), and integrated 2.5D and 3D packaging. Samsung’s foundry overview lists the company’s process and packaging offerings.
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This structure creates both an opportunity and a complication. Samsung can coordinate logic, memory and packaging within one corporate group, but external customers may also assess whether they are comfortable placing designs with a company that has its own chip-design businesses. That is a question of customer confidence, not evidence that a specific conflict is currently blocking business.
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GAA and the 2 nm transition
Samsung’s most important transistor-architecture bet is GAA. In a GAA transistor, the gate surrounds the channel on all sides, rather than controlling it from three sides as in a FinFET. Better electrostatic control can help reduce leakage and improve power efficiency as devices scale. Nanosheet implementations can also give designers more ways to tune channel width and balance performance against power.
Those potential benefits are not automatic. GAA makes process integration and manufacturing control more demanding, and can require tighter tolerances, mature design rules and well-developed libraries. A transistor architecture only matters commercially if it delivers competitive power, performance, area, yield and cost for real customer designs. Samsung was an early major foundry to introduce GAA with its 3 nm generation, but the fact of early introduction alone does not establish better yields or a better customer outcome.
Samsung’s current roadmap centers on the SF2 family, its 2 nm process generation. The company said it planned to ramp mobile products based on second-generation 2 nm in the second half of 2026, alongside expansion of 4 nm low-power and base-die products for AI and high-performance computing. Its Q2 2026 results also reported that advanced-node lines were running at full utilization and described expanding customer engagements. Those are company updates and outlook, not a full public account of yield, wafer economics or production volumes.
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Samsung is also reported to be planning SF2-family refinements, including a future SF2Z variant with backside power delivery. Moving power distribution to the back of the wafer could reduce congestion in front-side signal wiring and improve power delivery, but it adds challenging processing, alignment and thermal-management steps. No commercial yield or performance advantage should be assumed without measured production data.
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Node names are not ruler measurements
“2 nm” and “1.4 nm” are process-generation labels, not literal measurements of every transistor feature. Different foundries use their own naming conventions, so the number is not a reliable standalone ranking of physical dimensions. For customers, the useful comparison is how a process performs on a particular design, including power, performance, die area, yield, cost, schedule and available capacity.
EUV, high-NA and the work beyond lithography
Samsung says it introduced extreme ultraviolet (EUV) lithography from its 5 nm generation onward. EUV can reduce the need for some multiple-patterning steps used with older deep-ultraviolet approaches, but it does not make advanced manufacturing simple. Deposition, etch, masks, photoresists, metrology, defect inspection, transistor formation, interconnect resistance and yield learning all remain critical.
High-NA EUV is a future lithography platform, not proof that a company can already manufacture a commercial 1 nm-class process. A 2026 report on Samsung’s roadmap associated high-NA EUV with 1 nm-class and smaller technologies from around 2030 onward; that is reported roadmap guidance, not an independently verified production result. Lithography equipment is only one part of process capability.
Why packaging and HBM matter to AI chips
For AI accelerators and other high-performance chips, the product is increasingly a package-level system rather than a single logic die. 2.5D integration places multiple dies side by side and connects them through an interposer or bridge. 3D integration stacks dies vertically; hybrid bonding can enable dense die-to-die connections. These approaches can bring logic, HBM and other chiplets closer together, improving bandwidth and reducing the distance data must travel. They also add testing, thermal, assembly and yield challenges.
HBM is relevant to a foundry because a high-performance memory stack is only one element of the system. The package also needs a logic base die, high-speed connections and carefully managed power and heat. Samsung said it planned to expand 4 nm base-die and low-power products for AI/HPC applications. Its potential advantage is the ability to coordinate HBM, logic and advanced packaging—along with its research and manufacturing capabilities—rather than sell only wafer processing.
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That one-stop pitch could reduce handoffs between suppliers and help customers plan the package as a whole. It is not automatically superior to a more modular supply chain: multiple business divisions can create scheduling and allocation complexity, while customers may value a pure-play foundry’s commercial neutrality. Samsung markets 2.5D and 3D packaging, including its X-Cube 3D technology; the value of these offerings will depend on qualified products, capacity and customer results, not just a technology name.
AI, networking and other markets Samsung is pursuing
Samsung identifies AI/HPC, mobile, automotive, aerospace and silicon photonics among its areas of focus. These markets differ in what they reward:
- AI and HPC: high-value opportunities, but customers demand proven performance, power efficiency, packaging capacity, reliable schedules and mature design support. Demand can also be concentrated in a small number of buyers and programs.
- Mobile: a natural area for Samsung because it also designs processors and makes smartphones, but competition is intense and demand is cyclical.
- Automotive: long qualification and reliability requirements can support durable programs, but they generally slow adoption of new process generations.
- Aerospace and defense: trusted or geographically diversified supply may matter, but qualification, procurement and export-control requirements complicate entry.
- Silicon photonics: a possible response to data-center bandwidth and energy constraints. Samsung’s public materials describe foundational work, but do not establish the scale or commercial maturity of this business.
Samsung’s Q1 2026 investor presentation described diversification into AI/HPC, automotive and aerospace and a silicon-photonics foundation. That signals strategic intent, not established market share. The Q1 2026 presentation also described advanced-node utilization and customer expansion.
Customer announcements: engagement is not the same as volume
Foundry business develops through several stages: a customer evaluates a process, completes design work and tape-out, qualifies the product, enters production, then places repeat orders. A design win is useful evidence of interest, but it does not prove high-volume manufacturing or profitability.
Tesla: Samsung disclosed on a 2025 earnings call that it had won a $16.5 billion order for a next-generation Tesla product based on advanced process technology; it did not disclose the full contractual terms. A 2026 report said Tesla’s AI5 chip had taped out at Samsung and was expected to enter production at Taylor, but that production detail was secondary reporting rather than a complete official confirmation from Samsung or Tesla. The order is meaningful evidence of customer engagement, not a guarantee of timing, volume, Taylor utilization or broad customer diversification. Samsung’s 2025 earnings-call transcript contains the order disclosure; the AI5 report is a separate secondary account.
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Broadcom: Samsung and Broadcom announced a July 25, 2026 memorandum of understanding covering memory, foundry technologies at 2 nm and below, and advanced packaging. The companies estimated more than $200 billion of collaboration across memory and foundry through 2030. An MOU and an estimated collaboration value are not the same as finalized production orders or booked revenue. The announcement is evidence of strategic engagement in AI and networking infrastructure, not evidence that Samsung has displaced TSMC. Samsung’s announcement describes the MOU.
For a clearer read on commercial progress, watch for named products, qualified production, volume shipments, repeat orders, customer comments on performance and yield, and package-level launches. Utilization and revenue trends matter too, but Samsung does not publish a complete standalone foundry profit and yield picture.
Taylor, Texas: diversification with a demanding ramp
Samsung’s planned Taylor, Texas, facilities are intended to support leading-edge logic production and research in the United States. The U.S. Department of Commerce awarded Samsung Austin Semiconductor up to $4.745 billion in direct CHIPS Act funding. The project is expected to involve more than $37 billion in regional investment, two leading-edge logic fabs, an R&D fab, expansion of Austin operations and more than 15,000 total jobs, including construction and manufacturing employment. NIST lists the facilities as expected to be operational by 2030. These are project expectations and government timelines, not guarantees that every facility will be producing at full commercial utilization by then. See NIST’s project description and Samsung’s Taylor page.
A U.S. footprint can help Samsung appeal to customers seeking geographic diversification, including some government, automotive, aerospace and AI buyers. But “made in the United States” does not mean every part of the supply chain is domestic: equipment, materials, chemicals, design tools, packaging inputs and other resources remain globally sourced. Taylor must still clear construction, equipment installation, workforce recruitment, supplier development, utility, customer qualification and yield-ramp hurdles.
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Samsung versus TSMC: the customer’s scorecard
TSMC is the practical benchmark because it combines advanced-node manufacturing with a large customer ecosystem and extensive packaging capabilities. TSMC’s 2025 annual report said its N2 process entered high-volume manufacturing in the fourth quarter of 2025, with a rapid ramp expected in 2026; it also highlighted CoWoS, InFO and SoIC packaging. Those are TSMC’s own statements. The annual report is the source for its process and packaging disclosures.
| Consideration | Samsung Foundry | TSMC |
|---|---|---|
| Business model | Part of a group with foundry, memory and chip-design businesses | Primarily a pure-play foundry |
| Advanced transistors | Early GAA adoption; SF2 ramp and future SF1.4 roadmap | N2 GAA process reported in high-volume manufacturing from Q4 2025 |
| Memory and packaging | Potential coordination advantage from Samsung memory, logic and packaging | Extensive packaging portfolio and customer integration |
| Customer perception | Must demonstrate dependable execution and reassure customers about neutrality | Pure-play structure is straightforward to explain to external customers |
| Geographic diversification | Austin and planned Taylor operations in the United States | Expanding Arizona manufacturing alongside its Taiwan base |
| Key test | Convert process and package offerings into reliable, profitable external volume | Manage capacity, cost, geopolitics and packaging demand while maintaining execution |
Neither node labels nor corporate structure alone decides a customer’s choice. Buyers evaluate performance per watt, yield, wafer price, capacity, design tools and IP libraries, packaging, schedule reliability, customer service, geopolitical exposure and total cost of ownership. Samsung’s integration can be valuable to a customer seeking a coordinated memory-and-logic package; TSMC’s scale and pure-play model can be attractive to one prioritizing a broad ecosystem and established execution.
The financial question: improvement is not a disclosed turnaround
Samsung’s Q2 2026 update said advanced-node lines were at full utilization, earnings improved before incentive-related provisions and the company targeted double-digit foundry revenue growth in the second half of 2026. It also described growing U.S. customer design wins, including 2 nm HPC engagements. Those statements support a view of improving activity, but Samsung does not report a complete standalone foundry operating-profit line. Readers cannot infer foundry profitability from utilization or revenue growth alone.
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The more persuasive evidence of a durable improvement would be a combination of sustained revenue growth, repeat production from external customers, dependable delivery, better transparency around foundry economics, and profitable use of new capacity. Samsung’s current public commentary is encouraging on utilization and engagement, but does not disclose enough to independently verify all of those conditions.
Three plausible paths from here
- Bull case: SF2 yields stabilize, customer programs move from engagement to volume, Samsung converts AI/HPC opportunities into repeat business, and its HBM-plus-logic packaging offer proves valuable. Taylor ramps on schedule and attracts enough demand to justify its cost.
- Base case: Samsung becomes a credible second source for selected AI, mobile, automotive and specialty workloads, while TSMC retains broader leadership in scale, ecosystem and advanced-node execution.
- Bear case: yield or schedule setbacks, limited customer conversion and concentration in a few programs combine with high U.S. costs to leave Samsung with advanced technology but too little profitable external volume.
These are scenarios, not forecasts with assigned probabilities. The evidence that would shift the outlook is concrete: qualified products, shipments and repeat orders; reliable capacity and schedule performance; package-level customer launches; and Taylor’s operational ramp.
Quick Recap
What to watch next
- SF2 production evidence: whether second-generation 2 nm products reach sustained production, not merely a planned ramp.
- Customer conversion: whether announced engagements and tape-outs turn into qualified products, shipments and repeat orders.
- Packaging execution: whether Samsung can deliver integrated logic, HBM, base dies and advanced packaging at the scale AI customers need.
- Taylor readiness: progress on facilities, equipment, workforce, suppliers and customer qualification against the expected 2030 timeline.
- Economics and transparency: whether utilization and revenue growth translate into sustainable foundry margins—something difficult to assess fully without standalone profit disclosure.
- Roadmap discipline: whether future node dates remain credible and are supported by process and customer evidence rather than labels alone.
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