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On October 18, 1999, Lam Research announced that Taiwan Semiconductor Manufacturing Company (TSMC) had qualified Lam’s Teres integrated chemical mechanical planarization (CMP) and post-CMP cleaning system for its 0.18-micron copper CMP processes. Lam said Teres was the first system qualified for copper CMP at TSMC and that the foundry had designated it a production tool of record for copper processes. That was a specific manufacturing milestone—not evidence of adoption across every TSMC fab, copper layer, or later process generation.
What TSMC’s qualification meant
Lam said its joint-development qualification project with TSMC began in March 1999. In the October announcement, the company reported that TSMC’s evaluation found Teres met or exceeded specifications for dishing, erosion, total metal loss, and resistance non-uniformity. Dr. S. Y. Chiang, identified in the release as TSMC’s vice president of research and development, said the system met or exceeded those requirements and that TSMC expected to ramp quickly to copper production. Lam’s October 18, 1999 announcement is the source for those customer-performance statements.
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In manufacturing, evaluation means a tool is assessed; qualification means it has satisfied specified customer and process requirements. A “production tool of record” designation goes further: it identifies the selected reference tool for the stated production process. Here, the scope in the announcement is TSMC’s 0.18-micron copper CMP processes. The wording does not establish use across every fab, product, copper layer, or subsequent node, nor does it disclose installation count or duration of use.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsWhy copper CMP mattered
Copper interconnects are formed using damascene processing: patterned features are filled with copper, then excess material is removed and the wafer surface is planarized. CMP performance matters because uneven removal can leave copper recessed, thin the surrounding dielectric, or create surface variation that complicates subsequent processing. Those effects can influence electrical resistance and process integrity.
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The 0.18-micron phrase refers to a process generation as used in the period, not a claim that every physical feature in the process measured 0.18 micron. The qualification was for copper CMP, not for CMP generally or for other Teres applications.
The four performance measures TSMC cited
- Dishing: Recessing of copper features during polishing, potentially leaving the conductor lower than the surrounding surface.
- Erosion: Excessive thinning or removal in patterned regions, including the surrounding dielectric.
- Total metal loss: Unwanted removal of copper during the polishing process.
- Resistance non-uniformity: Variation in electrical resistance associated with inconsistent processing across the measured material.
These terms explain the process concerns behind the acceptance criteria; the public announcement does not provide numeric limits, measurement protocols, or underlying test data.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What Teres combined
Teres was an integrated CMP system paired with post-CMP cleaning. Lam described its polishing approach as Linear Planarization Technology (LPT) and identified the Synergy Integra post-CMP clean module, with its Performa feature set for copper cleaning. Integrating polishing and cleaning addressed two sequential needs: remove excess material to achieve planarity, then clean the wafer after polishing.
Lam said LPT was designed to optimize wafer uniformity, planarity, dishing, erosion, total oxide loss, and total metal loss. The company also claimed rotary systems could be optimized for selected parameters but could not match Teres across all of them on a single wafer. That comparison is Lam’s vendor claim; the announcement does not include independent comparative measurements.
What the historical record confirms—and leaves open
EDN reported the qualification on October 19, 1999, including the production-tool-of-record designation and the 0.18-micron copper CMP scope. Its brief contemporaneous report supports that this was treated as an industry news event, but it largely follows Lam’s announcement rather than presenting a separate technical audit. EDN’s report is dated one day after Lam’s release.
The public announcement does not state the specific TSMC fab or line, number of tools, throughput, yield effect, defect density, operating cost, maintenance intervals, copper stack, or exact process-integration flow. It also does not identify competing tools or establish how long Teres remained in production. Those details cannot be inferred from the qualification or the tool-of-record designation.
Lam later referred to Teres as TSMC’s tool of record for 0.18-micron copper CMP in a November 2, 1999 statement, providing near-term corroboration of the designation: Lam’s November 2, 1999 statement. That later reference does not broaden the qualification’s stated scope.
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