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Intel and SoftBank Corp.’s wholly owned SAIMEMORY subsidiary are collaborating on Z-Angle Memory (ZAM), a development-stage memory architecture designed for artificial-intelligence and high-performance-computing systems. The project is intended to combine high capacity, high bandwidth and lower power consumption, potentially addressing weaknesses in today’s high-bandwidth memory (HBM).
It is not, however, a newly formed Intel–SoftBank joint venture, a commercial product or a proven “HBM killer.” The companies are targeting a prototype in fiscal 2027 and commercialization in fiscal 2029—the Japanese fiscal year ending March 31, 2030. Those are development goals, not delivery guarantees.
What Intel and SoftBank are actually building
SoftBank Corp. announced on February 3, 2026, that SAIMEMORY and Intel had signed a collaboration agreement the previous day to commercialize Z-Angle Memory.
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ZAM is a proposed architecture rather than a finished memory chip or established industry standard. The official descriptions emphasize its potential to deliver:
- Higher memory capacity for large AI models and other demanding workloads;
- High data bandwidth between memory and processors;
- Lower power consumption; and
- Improved thermal behavior as memory is stacked vertically.
Why AI systems need new memory approaches
Modern AI accelerators can perform enormous numbers of calculations, but those calculations are useful only when data can reach the processor quickly enough. Memory bandwidth—the rate at which data can be transferred—often becomes a system-level constraint.
HBM addresses this problem by stacking DRAM dies and placing the memory close to an AI accelerator or other processor. Shorter connections and wide interfaces allow HBM to supply much more data than conventional memory in many accelerator designs.
HBM is already a commercial technology, but scaling it creates difficult trade-offs. More stacked layers and more complex packaging can increase:
- Heat density and the difficulty of removing heat;
- Manufacturing complexity and defective-stack risk;
- Advanced-packaging demand and cost;
- Interconnect and testing requirements; and
- Power consumption across memory, interfaces and surrounding circuitry.
Capacity is another constraint. An accelerator may have exceptional compute performance but still require multiple memory packages, external memory tiers or slower data transfers if its local memory cannot hold enough model weights and intermediate data.
That is the market opening ZAM is intended to address. Its success would depend not on one headline specification, but on whether it can deliver a useful balance of bandwidth, capacity, energy efficiency, thermal performance, yield, price and compatibility.
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How Z-Angle Memory is supposed to work
SAIMEMORY’s April 2026 technical announcement describes a vertically built memory structure using stacked DRAM and magnetic-field-coupled wireless I/O rather than relying solely on conventional wired connections between layers.
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That remains an engineering objective, not a publicly validated product result. The available announcements do not establish ZAM’s final bandwidth, capacity, latency, power consumption, manufacturing yield or reliability.
Wireless or magnetic-field-coupled I/O could also introduce new questions involving signal integrity, crosstalk, electromagnetic interference, error correction, latency, manufacturing tolerances and long-term operation across temperature changes. Those questions will need to be answered through prototypes and independent testing.
ZAM versus current HBM
| Category | Current HBM | Proposed ZAM |
|---|---|---|
| Basic memory | Commercial stacked DRAM | Proposed stacked-DRAM architecture |
| Main proposition | Very high bandwidth close to compute | High capacity, bandwidth and lower power consumption |
| Interconnect | Advanced packaging and die-to-die connections | Proposed magnetic-field-coupled wireless I/O |
| Commercial status | Established technology | Development-stage technology |
| Key uncertainty | Cost, heat, supply and packaging scale | Technical validation, yield and ecosystem adoption |
| Likely role | AI accelerators and HPC systems | Potential alternative or complement for AI and HPC |
ZAM should therefore be viewed as a possible alternative to, or complement for, HBM—not as an automatic replacement. HBM suppliers will also continue improving bandwidth, stack height, power efficiency, thermal design and cost. Faster HBM progress could narrow the commercial opportunity for a new architecture.
What Intel contributes
Intel brings semiconductor research and advanced-packaging expertise to the collaboration. Intel has connected the project with its Next Generation DRAM Bonding initiative, which focuses on improving performance and power efficiency in future DRAM designs.
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According to the Intel collaboration explanation, the work also relates to foundational technology validated through Intel’s participation in the U.S. Department of Energy’s Advanced Memory Technology program.
This gives Intel a route to participate in strategically important memory technology without demonstrating an immediate return to conventional commodity-DRAM manufacturing. Intel has previously reduced its exposure to other memory businesses, including selling its NAND and SSD business to SK hynix. The ZAM collaboration should not be described as proof that Intel has fully re-entered the DRAM market.
What SoftBank Corp. and SAIMEMORY contribute
SoftBank Corp. provides corporate backing and strategic interest in the memory required by future AI infrastructure. Its broader AI and data-center ambitions could potentially make it an early user or evaluation partner, although no guaranteed purchase volumes have been publicly established.
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That strategic support matters, but capital and a potential anchor customer do not by themselves establish a broad market. A commercially meaningful ZAM business would need adoption by multiple accelerator designers, cloud providers, server manufacturers and data-center operators.
The important April 2026 update
The project gained additional institutional support in April 2026.
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SAIMEMORY announced that it, Intel and RIKEN had been selected for a NEDO-backed development project. SAIMEMORY is the lead organization, Intel is a joint contractor and RIKEN is participating as a collaborative research institution.
RIKEN also invested in SAIMEMORY on March 27, 2026, with the investment announced April 22. The research organization plans to help design a ZAM performance-evaluation system drawing on its experience with supercomputing and memory-related workloads.
The disclosed Series A investors include Fujitsu, the Development Bank of Japan, RIKEN and SoftBank. NEDO backing and participation by major Japanese technology and research institutions improve the project’s resources and credibility. They do not prove that ZAM will achieve commercial manufacturing yields, meet its performance goals or secure customers.
Timeline and what has—and has not—been demonstrated
- December 2024: SoftBank Corp. establishes SAIMEMORY as a wholly owned subsidiary.
- February 2, 2026: SAIMEMORY and Intel sign their collaboration agreement.
- February 3, 2026: SoftBank Corp. announces the collaboration and ZAM objectives.
- March 27, 2026: RIKEN makes its investment in SAIMEMORY.
- April 22, 2026: SAIMEMORY announces the NEDO project, Series A investors and expanded institutional participation.
- FY2027: Prototype target, according to the official announcement. This means the fiscal year ending March 31, 2028.
- FY2029: Commercialization target, corresponding to the fiscal year ending March 31, 2030.
Publicly available announcements do not identify a commercial ZAM chip, independent benchmark results or a production-ready device demonstrating a 50% power reduction.
Earlier TechRepublic reporting cited a possible reduction of up to 50% in power consumption. That figure should be treated as an attributed expectation, not a verified result. A meaningful comparison would need to specify whether the reduction applies to power per transferred bit, a memory package, a complete workload or the entire system—and which HBM generation is used as the baseline.
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Bandwidth and capacity
ZAM must show that it can supply the bandwidth required by large AI accelerators, rather than merely offering more capacity at lower speed. Capacity claims must also be separated by package, stack, module and complete system.
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Energy and cooling
Lower memory-device power would be valuable, but it may not translate into lower total data-center energy if the architecture requires additional controllers, conversion circuitry, packaging or cooling. Sustained AI workloads are particularly important because thermal advantages that appear in short demonstrations may weaken under continuous operation.
Manufacturing yield
A technically successful prototype can still fail commercially if too many stacked assemblies are defective or if the required equipment cannot operate at volume. Yield, testing and repair strategies will be central to the cost-per-bit calculation.
Packaging and compatibility
ZAM will need to work with accelerator dies, substrates or interposers, package assembly, memory controllers, testing systems, server boards and existing data-center architectures. A new memory approach can be fast in isolation but difficult to adopt if it requires a complete ecosystem redesign.
Reliability
Customers will need evidence that magnetic-field-coupled links and stacked structures remain reliable over temperature, time and manufacturing variation. Qualification cycles for AI infrastructure can be long, particularly when a failure could disrupt an expensive data-center system.
Cost and supply
The commercial comparison is not simply the price of a memory chip. It includes cost per gigabyte, cost per unit of bandwidth, advanced packaging, cooling, yield losses, system redesign and the availability of qualified suppliers.
Why the project could matter to the market
If ZAM reaches production and delivers its intended combination of capacity, bandwidth and efficiency, it could give AI-system designers another option as HBM demand grows. It could also create pressure on existing memory and packaging suppliers by changing how memory is integrated with accelerators.
The project is strategically relevant to Japan because it links SoftBank Corp., RIKEN, Fujitsu, the Development Bank of Japan and NEDO with an advanced-memory development effort. For Intel, it offers participation in a critical AI-infrastructure component and a potential use for its memory-bonding and packaging research.
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But government support does not eliminate commercial risk, and AI demand does not guarantee adoption. Buyers will still require validated performance, dependable supply, software and hardware compatibility, competitive economics and a credible long-term roadmap.
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