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Sandra Rivera became chair of French fabless semiconductor company VSORA’s board on January 15, 2026. She did not become CEO: founder Khaled Maalej remains the operating chief. Rivera is joining as VSORA moves its Jotunn8 inference processor from a completed tape-out toward manufacturing, customer validation and commercial rollout.
What Rivera joined
VSORA appointed Rivera chair of its board of directors, with responsibilities spanning product-roadmap development, company infrastructure, product strategy, execution discipline, fundraising and go-to-market planning. The appointment was announced by VSORA on January 15, 2026 (company announcement).
That distinction matters. A board chair helps set direction, oversee management and support investors and partners; the role is not the same as running daily engineering, sales or operations. Maalej remains VSORA’s founder and CEO.
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Rivera spent more than two decades at Intel, from 2000 to 2023. She was executive vice president and general manager of Intel’s Data Center and AI Group, which covered Xeon CPUs, GPUs, FPGAs and AI accelerators. She also served as Intel’s chief people officer and led its Network Platforms Group.
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- ✅Powered by 26 Tera-Operations Per Second (TOPS) Hailo-8 AI Processor. 2.5W typical power consumption
- ✅Scalable, enabling simultaneous processing of multi-streams & multi-models
- ✅Enabling real-time, low latency and high-efficiency AI inferencing on the edge devices
- ✅Supports TensorFlow, TensorFlow Lite, ONNX, Keras, Pytorch frameworks
- ✅Supports Linux and Windows. Supports the temperature range of -40°C to 85°C
Most recently, she led Altera through its separation from Intel in a transaction involving Silver Lake Partners. In other words, “former Altera CEO” describes leadership of the FPGA business as it became an independent company; Rivera did not found Altera or spend her entire career at a standalone Altera. She also serves on the board of Equinix and on the advisory board of the UC Berkeley College of Engineering, according to VSORA’s announcement.
Her experience maps to VSORA’s immediate challenges: turning a chip design into a supported product, building relationships with cloud and systems companies, raising substantial capital and managing a transition from technical development to commercial execution.
What VSORA does
Founded in 2015, VSORA is a French fabless semiconductor company developing processors and silicon architectures for AI inference, data centers, edge AI, autonomous driving and robotics (company profile). It has roots in automotive and edge-oriented products, then shifted significant attention toward data-center inference while retaining architecture and customer-validation experience from Europe, the United States and Japan, according to Rivera’s interview with EE Times (EE Times).
Inference, not training
Training builds or refines a model. Inference runs that trained model to answer a query, generate text, classify information or make a prediction. VSORA is positioning its architecture primarily for inference, where customers care about response latency, sustained throughput, power and cost per query or token.
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The memory-wall problem
Large-model inference can be limited less by arithmetic than by moving model weights and intermediate data to the compute engines quickly enough. This bottleneck is commonly called the memory wall. VSORA says a combination of large high-bandwidth memory, chiplets and inference-focused architecture is intended to reduce that constraint. That is an architectural objective, not proof that the company has solved the industry-wide problem.
What Jotunn8 is supposed to deliver
Jotunn8 is VSORA’s flagship data-center inference processor. Company materials and Rivera’s EE Times comments describe the following design:
| Characteristic | Reported detail |
|---|---|
| Design | Chiplet-based processor |
| Process | TSMC 5-nanometer fabrication |
| Packaging | Advanced multi-chip packaging involving Global Unichip Corp. (GUC) |
| Memory | Eight stacks of HBM3, totaling 288 GB, according to Rivera |
| Compute rating | Approximately 3,200 teraflops, as stated by VSORA |
Large HBM capacity could let a system keep more of a model close to the compute units and reduce partitioning between devices. Chiplets can help combine large designs and manufacturing technologies. Neither feature, by itself, establishes superior real-world throughput, power or total cost.
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Where the chip stood by August 18, 2026
The milestones show a move from design work into production activity, but they do not establish broad deployment.
| Date | Development |
|---|---|
| April 29, 2025 | VSORA announced a $46 million round to support Jotunn8’s production phase (announcement). |
| October 22, 2025 | The company announced a successful Jotunn8 tape-out (announcement). |
| January 15, 2026 | Rivera became board chair. |
| February 17, 2026 | EE Times reported that first samples were expected in time for possible MLPerf inference submissions later in the summer; the rest of 2026 was expected to focus on ecosystem partners, cards and systems aimed at a 2027 ramp. |
| May 26, 2026 | GUC announced a Jotunn8 showcase at the TSMC Europe Technology Symposium (release archive). |
| July 1, 2026 | VSORA said Jotunn8 was entering manufacturing and commercial rollout after new funding led by Ardian (announcement). |
The defensible status is therefore: VSORA says Jotunn8 has moved from successful tape-out into manufacturing and commercial rollout. Available material does not independently establish broad availability, hyperscale deployment, Nvidia-beating results or validated MLPerf leadership.
Why the board appointment is strategically timed
Rivera told EE Times that her priorities include raising VSORA’s profile, helping raise capital, shaping go-to-market plans and keeping a small company from becoming overstretched across too many markets. Her background may help with:
- enterprise and cloud-infrastructure relationships;
- partnering across silicon, packaging, servers and software;
- capital formation for manufacturing and customer support;
- organizational processes needed after tape-out; and
- positioning an inference accelerator within heterogeneous systems rather than selling it as a universal replacement for every processor.
For a semiconductor startup, a successful tape-out is an engineering milestone, not the end of the business. Sampling, qualification, software enablement, supply commitments and repeat orders determine whether a design becomes a product.
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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsThe European angle—and its limits
VSORA presents itself as a European alternative in a market led by U.S. companies such as Nvidia and AMD. It is French, has received European Innovation Council support and lists investors or strategic participants including Ardian, Otium, XAnge, NJJ Capital, Capgemini through ISAI Cap Venture, CloudHQ and SPRIND in the July 2026 funding announcement.
Rank #4
- ✅Powered by 26 Tera-Operations Per Second (TOPS) Hailo-8 AI Processor. 2.5W typical power consumption
- ✅Scalable, enabling simultaneous processing of multi-streams & multi-models
- ✅Enabling real-time, low latency and high-efficiency AI inferencing on the edge devices
- ✅Supports TensorFlow, TensorFlow Lite, ONNX, Keras, Pytorch frameworks
- ✅Supports Linux and Windows. Supports the temperature range of -40°C to 85°C
The company says a French base could help it pursue European sovereign-AI and public-sector infrastructure opportunities. But “European AI-chip company” should not be confused with a fully European supply chain: the announced ecosystem includes Taiwan-based TSMC for fabrication and GUC for advanced implementation, while HBM and packaging remain globally sourced.
How VSORA says it differs from Nvidia and AMD
VSORA is not claiming to reproduce the breadth of Nvidia’s or AMD’s accelerator platforms. Its intended differentiation is narrower:
- inference specialization rather than broad training and general-purpose acceleration;
- large memory capacity for sizable models;
- low latency and sustained throughput;
- potentially lower power and cost per token; and
- use as one component in a heterogeneous data-center architecture.
That positioning separates three questions. The first is technical: what workloads the architecture is designed to optimize. The second is commercial: whether server builders and data-center operators will adopt it. The third is evidentiary: whether independent tests, software compatibility, availability and total cost of ownership confirm the pitch.
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What customers and investors still need to verify
- Independent performance and power measurements, including MLPerf or comparable results.
- Supported model architectures, precisions and quantization formats.
- Compiler, runtime, library and monitoring maturity.
- Compatibility with existing servers, networking and orchestration tools.
- Development boards, production cards and volume availability.
- HBM supply, packaging capacity, manufacturing yield and reliability.
- Customer references and production deployments.
- Total cost of ownership on representative workloads, not only peak teraflops.
- Security, support and product-lifecycle commitments.
Inference specialization may improve efficiency on selected models while offering less flexibility for training, fine-tuning, simulation or rapidly changing architectures. A 288 GB HBM figure does not by itself prove better economics, and peak compute does not predict latency without knowing precision, batch size, sequence length, utilization, memory access and interconnect behavior.
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- EDGE AI ACCELERATION: Designed to accelerate deep learning inference at the edge, enabling real-time AI applications without relying on cloud connectivity.
- RADXA AICORE MODULE: The Radxa AICore DX-M1M delivers a plug-and-play AI compute solution ideal for robotics, smart cameras, and industrial automation.
- WARRANTY AND ORIGIN: Backed by a 1-year manufacturer warranty and crafted with quality components for reliable long-term performance in demanding environments.
Claims that remain company projections
VSORA’s descriptions of Jotunn8 as the “world’s most powerful” or “Europe’s most powerful” inference chip, along with claims of more than three times the performance, less than half the power, unmatched scalability, a top-three global position or a unique European offering, come from company-controlled materials. They should be read as positioning or projections until independently reproduced.
The same caution applies to projected cost-per-query or cost-per-token advantages and any assertion that Jotunn8 can run models competitors cannot. Tape-out, manufacturing, sampling, qualification, deployment and volume production are separate milestones; the published record through August 18, 2026 reaches the first stages of that sequence, not proof of widespread production use.
The Bottom Line
Rivera’s appointment signals that VSORA is trying to become a commercial data-center semiconductor company, not merely complete an ambitious chip design. Her Intel and Altera experience could strengthen fundraising, partnerships and execution as Jotunn8 enters manufacturing. It does not, however, establish that the processor has displaced incumbent accelerators or achieved production-scale customer adoption.
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