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Cadence Design Systems acquired Altos Design Automation on May 10, 2011. The completed deal brought Cadence a specialist in characterizing foundation IP—the memory and standard-cell building blocks used in system-on-chip designs. The companies did not disclose the purchase price. Cadence’s announcement described the acquisition as an extension of its Silicon Realization offering.
What Altos did
Altos was an electronic-design-automation (EDA) company based in Campbell, California—not a chip manufacturer. It developed software to characterize foundation IP, including memory and standard-cell libraries, and generate models that designers could use in a system-on-chip (SoC) flow.
Characterization is an upstream modeling step, not the same thing as designing or physically implementing a chip. In a simplified flow, a semiconductor company characterizes a library under different operating conditions, producing timing, power, noise, and related models. Downstream tools use those models for tasks such as synthesis, timing analysis, physical implementation, and signoff. Better models can reduce uncertainty and rework, although the announcement did not quantify any resulting improvement.
Contemporaneous materials identify Altos products called Liberate and Variety. Cadence said Altos’s technology could improve visibility into timing, noise, and power across library creation, extraction, SPICE simulation, and implementation. Its announcement and contemporaneous coverage place the tools within the broader SoC design flow.
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Why Cadence wanted the technology
As process geometries shrank, variation and design complexity made accurate models more demanding to produce. Cadence’s strategic rationale was to automate and connect this specialized characterization work more closely with its broader design environment: characterize reusable IP, provide models to implementation tools, and help designers analyze timing, noise, and power earlier and with less manual iteration.
Cadence framed the purchase as an extension of its Silicon Realization portfolio and a step toward its then-current EDA360 vision. Those were the company’s strategic descriptions in 2011, not evidence that the acquisition delivered a measured productivity gain. The transaction’s rationale was vertical integration around a specific stage of the design flow, rather than the purchase of a broad, all-purpose chip-design platform.
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What the announcement disclosed
- Date and status: Cadence announced the acquisition on May 10, 2011, as a completed acquisition.
- Target: Privately held Altos Design Automation Inc., headquartered in Campbell, California.
- Price: Not disclosed; the available reporting does not support characterizing the deal as financially small or large.
- Customers: Cadence said Altos had more than 30 customers, including 11 of the top 20 semiconductor companies at the time. These are figures from Cadence’s announcement, not independently audited market data.
- Employees: Contemporary reporting said most Altos employees, including its founders, were expected to join Cadence. That describes the immediate plan, not long-term retention.
EE Times’ account reported that Altos was founded in 2005 by former Cadence and CadMOS Design Technology employees. Its reported founders included CEO Jim McCanny, CTO Ken Tseng, R&D vice president Kevin Chou, and R&D architect Wenkung Chu. Their prior Cadence experience helps explain the people-and-technology fit, but does not establish how long any individual stayed after the deal.
What is known about Altos after the deal
A patent record shows a 2012 assignment to Cadence involving technology associated with efficient library characterization. That supports the conclusion that at least some relevant Altos intellectual property moved to Cadence. It does not establish the full fate of every product or asset.
The available records do not provide an authoritative product-by-product history for Liberate or Variety. They are not enough to say whether either product was renamed, discontinued, continued under Cadence, or remains commercially available today. Nor do they establish the acquisition’s revenue contribution, return on investment, or long-term employee retention.
How to place the acquisition in context
The Altos deal is best understood as a 2011 EDA portfolio expansion: Cadence added a focused capability upstream of implementation, where models for reusable IP are created. It should not be confused with Cadence’s much later Hexagon design-and-engineering business acquisition, announced in 2025 and completed in 2026. That separate transaction was valued at approximately €2.70 billion; Altos’s price was undisclosed. Cadence’s Hexagon announcement documents the later deal.
In short, the historical significance of the Altos acquisition lies in the capability Cadence sought to add—not a disclosed price or a publicly documented post-deal product lineage. Cadence acquired a specialist whose characterization tools were intended to strengthen the models and analysis feeding advanced-node SoC implementation.
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