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3nm was never in danger of being abandoned simply because it was expensive. The 2018 warning was about the economics of designing and manufacturing leading-edge chips: one industry estimate put a complex 3nm design at roughly $1 billion. Commercial 3nm processes arrived, but the costs narrowed the field of products and companies able to justify them. The question is less whether 3nm works than whether its performance, density or power savings can repay the added design, manufacturing and packaging costs.
What the original 3nm warning meant
In June 2018, ExtremeTech published the warning that 3nm was “in jeopardy.” The concern was credible as an economic one: each new process generation demanded more investment in design, verification and manufacturing. It was not evidence that foundries would necessarily cancel 3nm. ExtremeTech’s original article is best read as a warning about who could afford advanced chips, rather than a prediction that the technology would not reach production.
That distinction matters to investors and businesses weighing semiconductor exposure. A process can be technically viable while being a poor financial choice for many products. 3nm became commercially available, with foundry process information published by TSMC and Samsung Foundry. Its economics are selective: premium and high-value products may support the investment, while less demanding chips can remain on older nodes or use a different architecture.
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“3nm” is a process-generation label, not a claim that every transistor or feature on a chip measures exactly three nanometres. A process generation combines changes to transistor structures, interconnects, design rules, density and performance characteristics. The details vary by foundry and process variant, so two products described as 3nm need not have identical design rules, libraries, density or performance.
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A newer node can let designers fit more logic into an area or target lower power or higher performance. It does not automatically make the finished chip cheaper. The result depends on such factors as die area, wafer pricing, yield, design expenses, package requirements and production volume. A smaller process can reduce cost per function while making the overall project more complex and expensive to finance.
How estimated design costs climbed
Industry estimates associated with IBS illustrate the steep curve. They are modeled estimates for advanced-chip design, not standard invoices or universal costs. Actual totals vary with product complexity, die size, existing intellectual property (IP), software, packaging, validation and the number of design revisions. A technical review reproduces the progression through 5nm and describes a 3nm design as potentially reaching about $1 billion; another review cites an estimate nearer $1.5 billion. Those different figures are a reason to treat 3nm costs as scenarios, not a precise price tag.
| Process node | Estimated advanced-chip design cost |
|---|---|
| 65nm | Approximately $28.5 million |
| 40nm | Approximately $37.7 million |
| 28nm | Approximately $51.3 million |
| 22nm | Approximately $70.3 million |
| 16nm | Approximately $106.3 million |
| 10nm | Approximately $174.4 million |
| 7nm | Approximately $297.8 million |
| 5nm | Approximately $542.2 million |
| 3nm | Approximately $1 billion projected in the historical estimate; other published estimates are higher |
These approximate figures are from the IBS-derived estimates discussed in a technical review. The reproduced IIC Journal chart and cost breakdown shows why “design cost” includes more than laying out transistors. The separate estimate of roughly $1.5 billion for 3nm, cited in an electronics review, reinforces that estimates depend on the scope and assumptions used.
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A headline number may aggregate spending across much of a product’s development cycle. Costs can include:
- Architecture and product definition
- RTL design, verification and validation
- Electronic design automation (EDA) software and engineering time
- Third-party semiconductor IP licensing and qualification
- Physical design, timing closure and design-for-manufacturing work
- Mask data preparation and photomask sets
- Prototype wafers, packaging and interposer development
- Silicon testing, engineering samples and production qualification
- Software and firmware enablement
- Respins, including new masks, wafers, engineering work and delayed revenue after a failed or marginal tape-out
Verification and validation become especially consequential as designs grow more complex. A successful tape-out—the handoff of a finished design for fabrication—does not by itself mean the chip will meet its targets, qualify for production or earn a return. Software, firmware, drivers and customer integration can also be major parts of getting a product to market.
Why smaller transistors do not guarantee a cheaper project
There are several different costs that are easy to conflate:
- Cost per transistor: the estimated expense associated with each transistor. A lower figure does not guarantee that a product’s total cost falls.
- Project cost: the fixed investment in design, tools, IP, masks, prototypes, validation and any respins.
- Cost per usable chip: affected by wafer cost, die area and the share of fabricated dies that pass testing.
- Cost per production unit: shaped by manufacturing and packaging costs and the volume over which fixed expenses are spread.
- Return on investment: whether the product’s price, sales, operating savings or strategic value repay those costs.
At advanced nodes, engineers face stricter design rules, harder timing closure, more specialized IP needs and challenging power-density and thermal constraints. More transistors can also mean more interactions to verify. If a large die has poor yield, the cost of each usable chip rises; if a late error forces a respin, the project needs more cash and time. A smaller node can improve cost per function and still raise the total amount of capital at risk.
The fab investment is a different cost from designing a chip
The historical analysis also estimated that a leading-edge fab could require roughly $15 billion to $20 billion at 3nm, compared with about $5.4 billion at 5nm and $2.9 billion at 7nm. These were historical estimates for a full leading-edge facility, not current universal construction prices. They are separate from a chip-design budget. The figures and their context are discussed in this historical analysis of fab investment.
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Building and operating a fab involves more than its cleanroom shell. Lithography, deposition, etch, metrology and inspection equipment are costly, as are utilities, process qualification, yield learning, maintenance and skilled staff. Capacity utilization matters: equipment and facilities must support enough production to justify the fixed investment.
Most fabless chip companies do not build a fab themselves. They pay foundries for manufacturing, but still face the associated economics through wafer prices, capacity commitments, masks, process qualification and packaging. Fab construction cost, design cost, wafer cost, package cost and per-chip cost are related but distinct figures.
When 3nm can make economic sense
A 3nm project is most plausible when the product can convert its technical advantages into enough value to cover development and manufacturing costs. Premium smartphone processors, data-center silicon, GPUs and AI accelerators are examples of categories where price, performance, power efficiency or differentiation may justify substantial investment. For large data-center deployments, power savings can have operating-cost value; for a product sold in high volume, fixed development costs can be spread across more units.
That does not make 3nm automatically worthwhile. The business case depends on whether the node delivers a measurable advantage for the intended workload and whether customers will pay for it. A company with reusable IP and mature design flows may face a different risk profile from a first-time customer building a large, complex chip. Foundry access, expected yield, market timing, software readiness and product lifetime also matter.
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A practical break-even test
A simplified way to frame the decision is:
Break-even units = NRE and fixed costs ÷ per-unit economic benefit
NRE means non-recurring engineering costs. The per-unit benefit is not necessarily a higher selling price. It can also include lower system cost, reduced power expense, higher performance value, a longer product life or avoiding a larger multi-chip solution. A fuller comparison should account for:
Total cost = design + masks + prototype wafers + packaging + validation + respins + yield loss + software enablement
There is no universal break-even volume. A small die with reusable IP and a strong margin can have a different equation from a large first-generation accelerator with uncertain demand. A calculation assuming one successful tape-out can also be too optimistic if a respin is plausible. Each additional spin can mean new masks and wafers, added engineering and validation, schedule delays and revenue that arrives later—or not at all.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Alternatives to putting the whole design on 3nm
| Option | When it may fit | Main trade-off |
|---|---|---|
| Stay on 5nm, 7nm or an older node | The product already meets its performance targets, volume is limited, or long qualification cycles make a process transition unattractive. Analog, RF, memory, I/O and high-voltage functions may also favor other process characteristics. | It may offer less logic density or worse power-performance for functions that benefit from a newer node. |
| Use chiplets and heterogeneous integration | Only some blocks need leading-edge logic, or smaller dies and reusable components could suit the product. | Advanced packaging, interconnects, testing, thermal management and system integration add cost and complexity. |
| Use an FPGA or adaptive SoC | Requirements may change, volumes are moderate, schedule matters, or avoiding an ASIC respin is valuable. | At high volume, programmable devices generally have higher per-unit cost and may use more power than a custom ASIC. |
| Reuse a platform across generations | A company can share CPU or GPU complexes, interface IP, verification environments, package footprints or chiplet fabrics across products. | Reuse requires up-front platform work and does not eliminate the need to validate each product and configuration. |
Older or mature nodes
Keeping a proven design on an older node can be sensible when its performance is sufficient, sales volumes do not support a costly redesign, or the product depends on analog, RF, high-voltage, memory or I/O characteristics that do not improve simply by moving to the newest logic process. The trade-off is that an older process may not provide the density or power-performance needed for a particular logic-heavy product.
Chiplets
Chiplets divide a system into separate dies. A design might put critical logic on an advanced node while keeping analog, I/O, SRAM or control functions on less expensive processes. Smaller dies can improve yield prospects, and validated components may be reused. This is not an automatic cost saving: advanced packages, interconnect latency and power, known-good-die testing, thermal design, standards and software integration can add expense. A review of chiplet and package co-design treats packaging as part of the scaling strategy, not a free substitute for monolithic design.
FPGA or adaptive SoC
Programmable logic can be attractive when flexibility and schedule are more valuable than the lowest unit cost. It can also reduce the risk of committing early to a fixed ASIC design. An AMD/Xilinx backgrounder gives an illustrative 5G-era ASIC-versus-FPGA total-cost crossover that could rise toward 250,000 units, depending on process and requirements; it also notes that additional ASIC revisions increase costs. That example is not a general threshold for other products or market conditions. See the AMD/Xilinx comparison.
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Reusable platforms
Shared IP, verification environments, package designs and configurable blocks can spread engineering effort across product generations and shorten later projects. Reuse is especially valuable because it can reduce schedule and redesign risk as well as direct development work. But the cost profile of a mature platform should not be compared with that of a first-time design as if both started from the same base.
Which projects face the most financial risk?
More exposed
- Low-volume or price-sensitive ASICs with little margin to recover fixed costs
- Products with uncertain demand or short market windows
- Large dies with challenging expected yield
- First-time designs without reusable IP or a mature design flow
- Projects requiring multiple custom accelerators or several design spins
- Companies that cannot secure suitable foundry capacity or package supply
- Products competing mainly on price, with little customer value from improved performance or power efficiency
Better positioned
- Premium smartphone, GPU, AI, data-center and networking products with strong potential margins or volumes
- Large platform businesses able to reuse IP, software and design infrastructure
- Products where energy savings materially reduce operating costs
- Automotive or industrial products with sufficiently high unit value and long-term demand to support development and qualification
- Designs where density or performance enables a product that would be impractical on an older node
These are financial profiles, not guarantees of success. Even a high-volume market can disappoint if a product misses its window, and a low-volume design can justify advanced silicon if each unit delivers unusually high value.
What the cost curve means for the industry
The central outcome was segmentation, not a simple victory or failure for 3nm. High-value logic can use the newest processes; cost-sensitive or specialized functions can remain on mature nodes; chiplets can combine dies built for different needs; and FPGAs can serve applications where adaptability matters. Advanced packaging is another route to system-level gains, but it shifts some expense and engineering effort from the die to the package and integration work.
For financial decision-makers, the useful question is not simply whether 3nm is affordable. It is whether a product’s measurable benefits can repay added engineering, manufacturing, packaging and schedule risk. The 2018 warning was directionally right about rising costs and increased pressure to choose carefully. It was not a verdict that 3nm could never be made or sold.
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