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On November 30, 2004, Applied Materials announced the Endura CuBS II, a physical-vapor-deposition (PVD) platform using new SIP EnCoRe II chambers for tantalum barrier and copper seed layers. Applied positioned it for “45nm and beyond,” but the public release identified qualification for 65nm production at an unnamed major chipmaker—not confirmed 45nm volume manufacturing.
What Applied Materials actually launched
The announcement concerned semiconductor-fabrication equipment and process chambers, not a 45nm processor or memory chip. The Endura CuBS II retained the Endura2 equipment base and added SIP EnCoRe II PVD chambers for copper-interconnect barrier and seed deposition. Applied said multiple chambers had shipped to customers in North America, Asia and Japan.
The company described dense, highly conformal tantalum barrier and copper seed films with reduced overhang in deep, narrow vias. The announcement also said the system was fully qualified and slated for 65nm production by a major chipmaker whose identity was not disclosed. See the November 30, 2004 announcement and its PDF copy.
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Barrier and seed layers: where they fit in copper wiring
Copper lowers interconnect resistance compared with aluminum, but it cannot simply be deposited directly against a silicon-dielectric structure. Copper can diffuse into surrounding materials, and the surface must be conductive and continuous before bulk copper is filled.
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- Barrier deposition: A thin tantalum-based layer, often tantalum or tantalum nitride in related process stacks, limits copper diffusion and supports adhesion.
- Seed deposition: A continuous copper film provides the electrical surface for subsequent electrochemical copper plating.
- Bulk fill: Plating deposits most of the copper volume in the trench or via.
- Planarization: Chemical-mechanical polishing removes copper outside the intended wiring pattern.
Applied’s earlier production material describes the barrier-and-seed stack and the role of Ta/TaN and copper films; its current Endura Amber explanation gives a later-generation description of the same basic integration problem. That later page should not be read as a specification sheet for the 2004 CuBS II.
Why scaling toward 45nm made PVD harder
As interconnect features shrink, vias and trenches become narrower and deeper relative to their opening. Conventional sputtering is partly line-of-sight: material tends to accumulate at the top corners before enough reaches the sidewalls and bottom.
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- Overhang: A thick lip forms around the via entrance.
- Pinch-off: The lip can constrict the opening before the bottom is covered.
- Seed discontinuity: Missing copper at the bottom or sidewall interrupts electroplating.
- Integration defects: Incomplete fill can create seams, voids, resistance variation and yield loss.
Applied said SIP EnCoRe II produced “CVD-like” conformal films with minimal overhang, including at the bottoms of deep, small vias. “CVD-like” described the coverage profile; the process remained PVD, not chemical-vapor deposition.
What SIP EnCoRe II was intended to improve
The release attributed the improvement to high-power-density sputtering sources. In practical terms, higher ionization and control of the sputtered species can make deposition more useful in high-aspect-ratio structures:
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- Diameter 3 inch by thickness 0.25 inch
- Purity 99.99%
- Cu:Ga 75:25 wt%
- More material reaches feature bottoms and sidewalls.
- Less material builds up at the opening.
- A continuous copper seed is more attainable before plating.
- A fab can extend a familiar PVD flow rather than immediately replacing it with a different deposition technology.
The public announcement does not provide independent thickness maps, step-coverage percentages, deposition rates, defect counts, electrical data or yield results. Those metrics should not be inferred from the “45nm” label.
What “45nm and beyond” meant in 2004
In 2004, 90nm production and 65nm development were major industry milestones. Applied’s wording presented CuBS II as an extendible platform for 45nm-class interconnect scaling. It did not identify a 45nm customer running volume production.
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- Diameter 3 inch by thickness 0.25 inch
- Purity 99.99%
- Cu:Ga 80:20 wt%
The most defensible reading is: Applied announced a PVD capability intended to support 45nm-generation copper interconnects, while publicly documenting 65nm production qualification. Node names describe a technology generation and design rules; they do not mean every barrier, seed or via dimension measured exactly 45nm.
Productivity and cost-of-ownership claims
Applied said SIP EnCoRe II doubled sputtering-target life to more than 20,000 wafers. Target replacement consumes maintenance time and materials, so a longer interval can improve tool availability and reduce ownership cost. The same release said Applied had shipped nearly 300 copper barrier/seed systems worldwide since 1998.
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- High purity, dense, small grains, low gas content sputtering targets
These are Applied Materials’ claims. The release does not publish an independent cost-per-wafer calculation, uptime study, target-utilization method or customer testimony. They should therefore be treated as vendor-reported performance and shipment figures, not audited market totals.
What a fab would evaluate beyond the headline
| Evaluation area | Why it matters | What the 2004 release establishes |
|---|---|---|
| Bottom and sidewall coverage | Determines whether plating receives a continuous seed. | Applied claimed dense, conformal films and low overhang; no public percentage was given. |
| Barrier continuity | Prevents copper diffusion into dielectric materials. | Tantalum barrier deposition was part of the announced process. |
| Electrical performance | Thin films preserve copper volume and limit resistance. | No independent resistivity or via-resistance dataset was published. |
| Defects and particles | Affect yield and reliability. | Not quantified in the announcement. |
| Target life and uptime | Influence maintenance frequency and cost. | Applied claimed more than 20,000 wafers and doubled target life. |
| Integration | Must work with preclean, plating, low-k dielectrics and CMP. | Platform compatibility was emphasized; complete integration data was not disclosed. |
Trade-offs in the deposition choice
PVD versus more conformal alternatives
PVD was mature and compatible with established production equipment, but shrinking aspect ratios made coverage increasingly difficult. CVD or atomic-layer-deposition approaches can offer stronger conformality, yet may add precursor, cost, throughput and integration complexity. SIP EnCoRe II represented an effort to push ionized PVD further rather than abandon it.
Barrier thickness versus resistance
A thicker barrier improves diffusion protection but leaves less volume for copper and can increase resistance. A thinner barrier reduces that penalty but raises the risk of discontinuities. The right thickness depends on the complete process integration, not the node name alone.
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Greater ionization and directional control can improve coverage, but engineers must also manage resputtering, film stress, dielectric damage, particles and defectivity. The 2004 announcement does not quantify those trade-offs for CuBS II.
Failure modes the technology had to address
- Seed discontinuity at via bottoms or sidewalls.
- Overhang and pinch-off at the via opening.
- Voids or seams during electrochemical fill.
- Copper diffusion through an incomplete barrier.
- High via or line resistance.
- Poor adhesion between dielectric, barrier, seed and plated copper.
- Low-k dielectric damage during surface preparation.
- Particles or target-related defects.
- Later electromigration and stress-migration failures.
- Confusing a process described as 45nm-capable with one qualified for 45nm volume production.
How CuBS II fits Applied’s copper roadmap
| Year | Milestone | Significance |
|---|---|---|
| 1999 | SEMATECH validated Applied’s Endura Electra copper barrier-and-seed system for production capability. | Established earlier production context. Source. |
| 2004 | Endura CuBS II with SIP EnCoRe II was announced for 45nm-and-beyond capability and 65nm qualification. | The subject of this article. Source. |
| 2005 | Applied reported more than 100 Endura CuBS systems shipped to 300mm fabs. | Shows continued commercial deployment. Source. |
| 2006 | Aktiv Preclean was announced for 45nm-generation copper/low-k integration. | Added surface preparation and low-k concerns; not a retroactive CuBS II specification. Source. |
| 2009 | CuBS RFX was announced with 32nm and 22nm production claims. | Illustrates subsequent PVD scaling. Source. |
Bottom line for technology and investment readers
CuBS II was a strategically important equipment announcement because it targeted the geometric limits of PVD copper barrier and seed deposition. Its SIP EnCoRe II chambers were presented as a way to improve coverage and reduce overhang while retaining a production-oriented Endura platform and longer target life. The evidence supports a 2004 launch aimed at 45nm-class scaling and qualified for 65nm production—not proof that Applied had already placed a named customer’s 45nm process into volume manufacturing.
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